公开(公告)号：US20090242865A1

公开(公告)日：2009-10-01

申请号：US12060075

申请日：2008-03-31

Applicant: Hsiang-Lan Lung ,  Min Yang ,  Thomas D. Happ ,  Bipin Rajendran

Inventor： Hsiang-Lan Lung ,  Min Yang ,  Thomas D. Happ ,  Bipin Rajendran

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L27/24

Abstract: A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.

Abstract translation: 一种制造存储器阵列的方法。 该方法由通常由介电填充材料构成并且在其下部形成有导电线的结构和在其上表面上形成的牺牲层开始。 在填充材料中形成二极管，每个二极管具有与导电线相同的导电类型的轻掺杂的第一层; 相反导电类型的重掺杂第二层; 和导电帽。 在二极管上形成自对准的通孔。 自对准和自对准的自对准通孔中的间隔物限定暴露导电盖的孔。 记忆材料沉积在孔内，记忆材料与导电帽接触。 形成与记忆材料接触的顶部电极。

公开(公告)号：US20140063925A1

公开(公告)日：2014-03-06

申请号：US13434739

申请日：2012-03-29

Applicant: Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

Inventor： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

Abstract translation: 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

公开(公告)号：US08558210B2

公开(公告)日：2013-10-15

申请号：US13449378

申请日：2012-04-18

Applicant: Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

Inventor： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

IPC: H01L45/00

CPC classification number: H01L45/148 ,  H01L27/0623 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

Abstract translation: 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。

公开(公告)号：US20130173516A1

公开(公告)日：2013-07-04

申请号：US13343371

申请日：2012-01-04

Applicant: Bipin Rajendran ,  Mark B. Ritter

Inventor： Bipin Rajendran ,  Mark B. Ritter

IPC: G06N3/063

CPC classification number: G06N3/0635 ,  G06N3/04 ,  G06N3/049

Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

公开(公告)号：US20130173515A1

公开(公告)日：2013-07-04

申请号：US13611722

申请日：2012-09-12

Applicant: Bipin Rajendran ,  Mark B. Ritter

Inventor： Bipin Rajendran ,  Mark B. Ritter

IPC: G06N3/04

CPC classification number: G06N3/0635 ,  G06N3/04 ,  G06N3/049

Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

Abstract translation: 根据技术，电子设备被配置为对应于生物突触的特征。 电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二 电子神经元。 电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。

公开(公告)号：US08350316B2

公开(公告)日：2013-01-08

申请号：US12471287

申请日：2009-05-22

Applicant: Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

Inventor： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

IPC: H01L29/732

CPC classification number: H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

Abstract translation: 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

公开(公告)号：US20120199806A1

公开(公告)日：2012-08-09

申请号：US13449378

申请日：2012-04-18

Applicant: Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

Inventor： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

IPC: H01L47/00

CPC classification number: H01L45/148 ,  H01L27/0623 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

Abstract translation: 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。

公开(公告)号：US08237144B2

公开(公告)日：2012-08-07

申请号：US13252152

申请日：2011-10-03

Applicant: Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

Inventor： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

IPC: H01L29/02

CPC classification number: H01L45/04 ,  G11C13/0004 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

Abstract translation: 本文描述了存储器件和制造方法。 本文描述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。 双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。 双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

公开(公告)号：US20120147666A1

公开(公告)日：2012-06-14

申请号：US12964980

申请日：2010-12-10

Applicant: Catherine A. Dubourdieu ,  Martin M. Frank ,  Bipin Rajendran ,  Alejandro G. Schrott

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Bipin Rajendran ,  Alejandro G. Schrott

IPC: G11C11/21 ,  H01L21/02

CPC classification number: H01L45/1608 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0095 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.

Abstract translation: 所公开的示例实施例是相变存储单元。 存储单元包括相变材料和位于相变材料附近的换能器。 相变材料可在至少非晶状态和结晶状态之间切换。 换能器被配置为当相变材料从非晶状态转变为结晶状态时激活。 在特定实施例中，换能器是铁电材料。

公开(公告)号：US20120018845A1

公开(公告)日：2012-01-26

申请号：US13252152

申请日：2011-10-03

Applicant: Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

Inventor： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

IPC: H01L29/73

CPC classification number: H01L45/04 ,  G11C13/0004 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

Abstract translation: 本文描述了存储器件和制造方法。 本文描述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。 双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。 双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。