利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

94 条记录 (耗时 0.026 秒)

    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS
    1.
    发明申请
    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS 审中-公开
    并行编程多相变化记忆细胞

    公开(公告)号：US20140063925A1

    公开(公告)日：2014-03-06

    申请号：US13434739

    申请日：2012-03-29

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

    摘要翻译： 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    2.
    发明申请
    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
    在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性

    公开(公告)号：US20120084241A1

    公开(公告)日：2012-04-05

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices
    3.
    发明授权
    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
    使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性

    公开(公告)号：US09269042B2

    公开(公告)日：2016-02-23

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Programmable delay element
    8.
    发明授权
    Programmable delay element 有权
    可编程延迟元件

    公开(公告)号：US07279949B2

    公开(公告)日：2007-10-09

    申请号：US11215416

    申请日：2005-08-30

    申请人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

    发明人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00039

    摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

    摘要翻译： 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

    Sub-rate low-swing data receiver
    9.
    发明授权
    Sub-rate low-swing data receiver 有权
    次速低音数据接收机

    公开(公告)号：US09240789B2

    公开(公告)日：2016-01-19

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

    SUB-RATE LOW-SWING DATA RECEIVER
    10.
    发明申请
    SUB-RATE LOW-SWING DATA RECEIVER 有权
    分数低速数据接收器

    公开(公告)号：US20150303920A1

    公开(公告)日：2015-10-22

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。