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    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS
    1.
    发明申请
    PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS 审中-公开
    并行编程多相变化记忆细胞

    公开(公告)号：US20140063925A1

    公开(公告)日：2014-03-06

    申请号：US13434739

    申请日：2012-03-29

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

    摘要翻译： 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    2.
    发明申请
    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
    在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性

    公开(公告)号：US20120084241A1

    公开(公告)日：2012-04-05

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices
    3.
    发明授权
    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
    使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性

    公开(公告)号：US09269042B2

    公开(公告)日：2016-02-23

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Compact low-power asynchronous resistor-based memory read operation and circuit
    4.
    发明授权
    Compact low-power asynchronous resistor-based memory read operation and circuit 有权
    紧凑型低功耗基于异步电阻的存储器读操作和电路

    公开(公告)号：US08824218B2

    公开(公告)日：2014-09-02

    申请号：US13552932

    申请日：2012-07-19

    申请人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C7/06

    CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

    摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

    摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

    Compact low-power asynchronous resistor-based memory read operation and circuit
    6.
    发明授权
    Compact low-power asynchronous resistor-based memory read operation and circuit 有权
    紧凑型低功耗基于异步电阻的存储器读操作和电路

    公开(公告)号：US08331164B2

    公开(公告)日：2012-12-11

    申请号：US12960651

    申请日：2010-12-06

    申请人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C7/06

    CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

    摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

    摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

    COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT
    7.
    发明申请
    COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
    紧凑型低功耗异步电动势记忆读取操作和电路

    公开(公告)号：US20120140554A1

    公开(公告)日：2012-06-07

    申请号：US12960651

    申请日：2010-12-06

    申请人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    发明人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/06

    CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

    摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

    摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

    COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT
    8.
    发明申请
    COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
    紧凑型低功耗异步电动势记忆读取操作和电路

    公开(公告)号：US20140078837A1

    公开(公告)日：2014-03-20

    申请号：US13552932

    申请日：2012-07-19

    申请人： SEONGWON KIM ,  Yong Liu ,  Bipin Rajendran

    发明人： SEONGWON KIM ,  Yong Liu ,  Bipin Rajendran

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

    摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

    摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。