公开(公告)号：US07875938B2

公开(公告)日：2011-01-25

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/51

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20100112797A1

公开(公告)日：2010-05-06

申请号：US12263091

申请日：2008-10-31

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/3205

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.

摘要翻译： 本发明涉及一种用于形成存储器阵列的方法。 该方法包括提供其上形成有电荷捕获结构的衬底的步骤。 图案化的材料层形成在衬底上，并且具有多个沟槽的图案化材料层暴露电荷俘获结构的一部分。 此外，在图案化材料层的沟槽的侧壁上分别形成多个导电间隔物，并且沟槽底部的电荷捕获结构的一部分被导电间隔物暴露。 在衬底上形成绝缘层以填充图案化材料层的沟槽。 此外，执行平面化处理以去除绝缘层的一部分，直到图案化材料层的顶表面和每个导电间隔物的顶表面露出。

公开(公告)号：US20100109076A1

公开(公告)日：2010-05-06

申请号：US12264879

申请日：2008-11-04

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L27/0251 ,  H01L29/7436

摘要： A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域，第二导电类型的第二阱区域，第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第一掺杂区域和第二导电类型的第二掺杂区域位于第二阱区域中。 第一晶体管包括第一掺杂区域，第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区，第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。

公开(公告)号：US07573102B2

公开(公告)日：2009-08-11

申请号：US11496490

申请日：2006-08-01

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

摘要翻译： 在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制 电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。 基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

公开(公告)号：US20090108345A1

公开(公告)日：2009-04-30

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/78

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20080266966A1

公开(公告)日：2008-10-30

申请号：US11782149

申请日：2007-07-24

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/26

摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

摘要翻译： 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US20080106274A1

公开(公告)日：2008-05-08

申请号：US11979576

申请日：2007-11-06

申请人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R27/26

CPC分类号： G01R31/2621

摘要： A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

摘要翻译： 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US06965504B2

公开(公告)日：2005-11-15

申请号：US10304137

申请日：2002-11-26

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H01L27/02 ,  H02H3/20

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.

摘要翻译： 用于高电压输入焊盘的ESD保护装置包括连接在输入焊盘和回弹装置之间的调制器，其具有围绕调制器的第一和第二保护环，围绕着快速恢复装置的第三保护环，以及第一和第二保护环控制电路 控制保护环，使保护装置在正常工作状态下具有较高的触发和保持电压，并在ESD事件下具有较低的触发和保持电压。

公开(公告)号：US20050237813A1

公开(公告)日：2005-10-27

申请号：US10876255

申请日：2004-06-24

申请人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

发明人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L29/7885 ,  H01L29/792

摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

摘要翻译： 提供了用于操作电荷捕获存储器单元的过程和存储器架构。 用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。 该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。 通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。 偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。 从而避免了过度擦除的情况。

公开(公告)号：US06829125B2

公开(公告)日：2004-12-07

申请号：US09938511

申请日：2001-08-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Sing Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Sing Su ,  Tao-Cheng Lu

IPC分类号： H02H900

CPC分类号： H01L27/0285

摘要： The invention discloses an ESD (Electro Static Discharge) protection circuit, including a resistor device, a capacitor device and a PMOS device. The resistor device is connected in series between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. A gate electrode of the PMOS device is connected between the resistor device and the capacitor device. A bulk electrode of the PMOS device is interconnected to a first electrode of the PMOS device, and the first electrode is connected to the power supply. Alternatively, another ESD protection circuit for multiple power supplies includes at least two aforementioned ESD protection circuits, and a common ESD bus. The ESD protection circuits are connected to separate power supplies, and both connected to the common ESD bus. By using the ESD protection circuit, there is no noise between the separate power supplies, and an ESD current could be discharged easily and safely.

摘要翻译： 本发明公开了一种ESD（静电放电）保护电路，包括电阻器件，电容器器件和PMOS器件。 电阻器件串联在电源和电容器之间。 电容器器件串联在电阻器件和地之间。 PMOS器件的栅电极连接在电阻器件和电容器器件之间。 PMOS器件的体电极互连到PMOS器件的第一电极，并且第一电极连接到电源。 或者，用于多个电源的另一ESD保护电路包括至少两个上述ESD保护电路和公共ESD总线。 ESD保护电路连接到单独的电源，并且都连接到公共ESD总线。 通过使用ESD保护电路，在单独的电源之间不存在噪声，并且ESD电流可以容易且安全地放电。