公开(公告)号：US20240063184A1

公开(公告)日：2024-02-22

申请号：US17889914

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay ,  Bang-Ning Hsu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06551 ,  H01L2225/06586

Abstract: A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

公开(公告)号：US20240055366A1

公开(公告)日：2024-02-15

申请号：US17888324

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L24/96 ,  H01L24/94 ,  H01L24/32 ,  H01L25/0657 ,  H01L21/565 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L2224/95001 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2924/37001 ,  H01L2924/35121 ,  H01L2924/3511 ,  H01L2924/3025 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/06537 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/183 ,  H01L2924/186 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431

Abstract: A semiconductor device assembly, including a lower semiconductor die; a stack of upper semiconductor dies disposed over the lower semiconductor die; a conductive package perimeter material surrounding the stack of upper semiconductor dies; and an encapsulant material disposed between sidewalls of the stack of upper semiconductor dies and the conductive package perimeter material, and horizontally extending between the conductive package perimeter material and the lower semiconductor die. A method of forming a plurality of semiconductor assemblies, including stacking a plurality of semiconductor die stacks on a device wafer; disposing a pre-formed spacer assembly structure including a spacer material and a conductive package perimeter material around each of the plurality of semiconductor die stacks; disposing an encapsulant material between the conductive package perimeter material of the pre-formed spacer assembly structure and the corresponding semiconductor die stack; and singulating the device wafer to form the plurality of semiconductor device assemblies.

公开(公告)号：US20240006320A1

公开(公告)日：2024-01-04

申请号：US18368987

申请日：2023-09-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/532 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L23/53238 ,  H01L23/481 ,  H01L25/50 ,  H01L23/3107 ,  H01L21/78 ,  H01L25/0657

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US20240006179A1

公开(公告)日：2024-01-04

申请号：US18469431

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/76859 ,  H01L21/78 ,  H01L21/26513

Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

公开(公告)号：US20230352413A1

公开(公告)日：2023-11-02

申请号：US18214378

申请日：2023-06-26

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L21/50 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/76877 ,  H01L25/0657 ,  H01L21/50 ,  H01L23/5386 ,  H01L21/486 ,  H01L21/76802

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

公开(公告)号：US11784092B2

公开(公告)日：2023-10-10

申请号：US16994941

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/268 ,  H01L21/683 ,  H01L21/02

CPC classification number: H01L21/78 ,  H01L21/02076 ,  H01L21/268 ,  H01L21/561 ,  H01L21/6836

Abstract: Singulated integrated circuit (IC) dice are provided. The singulated IC dice are positioned on dicing tape to provide open space between sides of adjacent singulated IC dice. An underfill layer and a protective cover film is disposed above the singulated IC dice and the open space between the sides of the adjacent singulated IC dice. The underfill layer and the protective cover film include one or more photodefinable materials. An exposure operation is performed to produce a pattern on the underfill layer and the protective cover film. Based on the pattern, the underfill layer and the protective cover film is removed at areas above the open space between the sides of the adjacent singulated IC dice to create portions of the underfill layer and portions of the protective cover film that are disposed above the singulated IC dice.

公开(公告)号：US20220344270A1

公开(公告)日：2022-10-27

申请号：US17237496

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L21/48 ,  H01L21/768

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

公开(公告)号：US11239129B2

公开(公告)日：2022-02-01

申请号：US17006740

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

IPC: H01L23/31 ,  H01L23/473 ,  H01L21/56 ,  H01L23/36 ,  H01L23/467

Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

公开(公告)号：US20210391316A1

公开(公告)日：2021-12-16

申请号：US16898180

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Bradley R. Bitz

IPC: H01L25/00 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

Abstract: A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

公开(公告)号：US20210343692A1

公开(公告)日：2021-11-04

申请号：US16864873

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: Methods for reducing heat transfer in semiconductor devices, and associated systems and devices, are described herein. In some embodiments, a method of manufacturing a semiconductor device includes forming a channel in a region of a substrate between a first die stack and a second die stack. The first die stack includes a plurality of first dies attached to each other by first film layers and the second die stack includes a plurality of second dies attached to each other by second film layers. The channel extends entirely through a thickness of the substrate. The method also includes applying heat to the first die stack to cure the first film layers. The channel reduces heat transfer from the first die stack to the second die stack.