公开(公告)号：US20210365268A1

公开(公告)日：2021-11-25

申请号：US16878226

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/1045 ,  G06F12/0868 ,  G06F13/16

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US11183266B2

公开(公告)日：2021-11-23

申请号：US16453905

申请日：2019-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F12/126 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04 ,  G06F12/0813 ,  G11C29/44 ,  H04L29/12 ,  G06F11/10 ,  G11C11/408 ,  G11C11/418

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US11009798B2

公开(公告)日：2021-05-18

申请号：US16122062

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  G01R33/07 ,  H01L23/544

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US20210098047A1

公开(公告)日：2021-04-01

申请号：US17121466

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  David Hulton ,  Jeremy Chritz

IPC: G11C11/406 ,  G06F11/10 ,  G11C29/02 ,  G11C29/52

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

公开(公告)号：US20200264688A1

公开(公告)日：2020-08-20

申请号：US16276461

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3206 ,  G06F11/34 ,  G06F11/30 ,  G06F11/00

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US20200073257A1

公开(公告)日：2020-03-05

申请号：US16122062

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  H01L23/544 ,  G01R33/07

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US20190305211A1

公开(公告)日：2019-10-03

申请号：US16434634

申请日：2019-06-07

Applicant: Micron Technology, Inc.

Inventor： Wei Chen ,  Witold Kula ,  Manzar Siddik ,  Suresh Ramarajan ,  Jonathan D. Harms

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16

Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

公开(公告)号：US20160329486A1

公开(公告)日：2016-11-10

申请号：US14706182

申请日：2015-05-07

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Wei Chen ,  Sunil S. Murthy ,  Witold Kula

IPC: H01L43/02

CPC classification number: H01L43/08

Abstract: A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first magnetic region, a second magnetic region spaced from the first magnetic region, and a third magnetic region spaced from the first and second magnetic regions. A first non-magnetic insulator metal oxide-comprising region is between the first and second magnetic regions. A second non-magnetic insulator metal oxide-comprising region is between the second and third magnetic regions. Other embodiments are disclosed.

Abstract translation: 磁性隧道结具有包括磁记录材料的导电第一磁极。 导电的第二磁电极与第一电极间隔开并且包括磁性参考材料。 非磁性隧道绝缘体材料位于第一和第二电极之间。 第一电极的磁记录材料包括第一磁性区域，与第一磁性区域间隔开的第二磁性区域和与第一和第二磁性区域间隔开的第三磁性区域。 第一非磁性绝缘体金属氧化物包含区域在第一和第二磁性区域之间。 第二非磁性绝缘体金属氧化物包含区域在第二和第三磁性区域之间。 公开了其他实施例。

公开(公告)号：US20250150276A1

公开(公告)日：2025-05-08

申请号：US19016412

申请日：2025-01-10

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: H04L9/32 ,  G06Q20/06 ,  G06Q20/38 ,  H04L9/00

Abstract: Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US20250085767A1

公开(公告)日：2025-03-13

申请号：US18957430

申请日：2024-11-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).