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公开(公告)号：US11431629B2
公开(公告)日：2022-08-30
申请号：US16991376
申请日：2020-08-12
Applicant: Micron Technology, Inc.
Inventor： Aleksei Vlasov , Prateek Sharma , Yoav Weinberg , Scheheresade Virani , Bridget L. Mallak
Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.
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62.发明申请公开(公告)号：US20220006473A1
公开(公告)日：2022-01-06
申请号：US17447864
申请日：2021-09-16
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Zhengang Chen , Sivagnanam Parthasarathy , Yoav Weinberg
Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.
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公开(公告)号：US20210182207A1
公开(公告)日：2021-06-17
申请号：US16713552
申请日：2019-12-13
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D`Eliseo , Carminantonio Manganelli , Paolo Papa , Yoav Weinberg , Giuseppe Ferrari , Massimo Laculo , Lalla Fatima Drissi
IPC: G06F12/1009
Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.
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公开(公告)号：US10983918B2
公开(公告)日：2021-04-20
申请号：US16294427
申请日：2019-03-06
Applicant: Micron Technology, Inc.
Inventor： Carminantonio Manganelli , Yoav Weinberg , Alberto Sassara , Paolo Papa , Luigi Esposito , Giuseppe D'Eliseo , Angelo Della Monica , Massimo Iaculo
IPC: G06F12/1009
Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.
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公开(公告)号：US20200210344A1
公开(公告)日：2020-07-02
申请号：US16294427
申请日：2019-03-06
Applicant: Micron Technology, Inc.
Inventor： Carminantonio Manganelli , Yoav Weinberg , Alberto Sassara , Paolo Papa , Luigi Esposito , Giuseppe D'Eliseo , Angelo Della Monica , Massimo Iaculo
IPC: G06F12/1009
Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.
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Patent Agency Ranking
公开(公告)号：US20250123925A1
公开(公告)日：2025-04-17
申请号：US18774464
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Mariano Eduardo Burich , Sivagnanam Parthasarathy , Phong Sy Nguyen , Yoav Weinberg
IPC: G06F11/10
Abstract: Methods, systems, and devices for page-by-page level shaping are described. The described techniques provide for a controller of a memory device to implement page-by-page level shaping when transferring data to a non-volatile memory device (e.g., flash memory). For example, the controller may receive a first set of bits associated with a first page of memory cells and may shape the first set of bits using a first shaping function to generate a second set of bits. Additionally, the controller may receive a third set of bits associated with a second page of memory cells and may shape the third set of bits using a second shaping function and the second set of bits to generate a fourth set of bits. In some cases, the controller may shape successive sets of bits using previously shaped bits and respective shaping functions.
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公开(公告)号：US20250021271A1
公开(公告)日：2025-01-16
申请号：US18782405
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
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公开(公告)号：US20240319873A1
公开(公告)日：2024-09-26
申请号：US18606794
申请日：2024-03-15
Applicant: Micron Technology, Inc.
Inventor： Raja V.S. Halaharivi , Yoav Weinberg
CPC classification number: G06F3/0608 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2212/7201
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: detecting an asynchronous power loss event at the memory device; receiving, from a host system, a memory access command; determining that a size of the memory access command satisfies a threshold criterion, wherein the threshold criterion corresponds to an atomic write unit size; responsive to determining that the size of the memory access command satisfies the threshold criterion, executing the memory access command using a hardware component of the memory device; and responsive to executing the memory access command, notifying the host system of completion of execution of the memory access command.
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公开(公告)号：US12088301B2
公开(公告)日：2024-09-10
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US20240235578A9
公开(公告)日：2024-07-11
申请号：US18048284
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
CPC classification number: H03M13/095 , H03M13/611
Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
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