公开(公告)号：US11735258B2

公开(公告)日：2023-08-22

申请号：US17711211

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Robert J. Gleixner ,  Karthik Sarpatwari

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0045

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.

公开(公告)号：US20230230642A1

公开(公告)日：2023-07-20

申请号：US18189824

申请日：2023-03-24

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US11688450B2

公开(公告)日：2023-06-27

申请号：US17186962

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E Fackenthal ,  Duane R. Mills

IPC: G11C11/404

CPC classification number: G11C11/404

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：US11665880B2

公开(公告)日：2023-05-30

申请号：US17003037

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/108 ,  G11C11/401

CPC classification number: H01L27/10802 ,  G11C11/401

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

公开(公告)号：US20230048450A1

公开(公告)日：2023-02-16

申请号：US17980382

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  John F. Schreck

IPC: G11C13/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04

Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

公开(公告)号：US20220392560A1

公开(公告)日：2022-12-08

申请号：US17337195

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Xuan-Anh Tran ,  Nevil N. Gajera ,  Karthik Sarpatwari ,  Amitava Majumdar

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

公开(公告)号：US11508437B2

公开(公告)日：2022-11-22

申请号：US17196638

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Nevil Gajera ,  Karthik Sarpatwari

IPC: G11C7/00 ,  G11C13/00

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

公开(公告)号：US20220319616A1

公开(公告)日：2022-10-06

申请号：US17845174

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

公开(公告)号：US20220319606A1

公开(公告)日：2022-10-06

申请号：US17221412

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/10 ,  G06N3/08 ,  G06N3/04 ,  G11C11/56 ,  G06F11/10 ,  G11C16/04

Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

公开(公告)号：US20220284973A1

公开(公告)日：2022-09-08

申请号：US17825941

申请日：2022-05-26

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.