公开(公告)号：US20240071902A1

公开(公告)日：2024-02-29

申请号：US17893718

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: Methods, systems, and devices for folded staircase via routing for memory are described. For instance, a memory device may include a set of word lines extending in first direction. Additionally, the memory device may include a first via, a second via, and a third via in a trench that extends through at least a portion of the set of word lines The first via, the second via, and the third via may extend in a second direction different than the first, where the second via is between the first via and the third via along the first direction, and where the second via is coupled with a word line of the set of word lines. Additionally, the first via and the third via may be electrically isolated from the word line of the set of word lines.

公开(公告)号：US11901292B2

公开(公告)日：2024-02-13

申请号：US17819019

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20230395501A1

公开(公告)日：2023-12-07

申请号：US18202061

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo

IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27

Abstract: Some embodiments include apparatuses. One of the apparatuses includes a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions; conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region; dielectric isolators separating the conductive islands from each other, wherein the conductive islands include a conductive island such that a first portion of the conductive islands is located on a first side of the conductive island, and a second portion of the conductive islands is located on a second side of the conductive island; and the width of the conductive island is greater than the width of at least one conductive island in each of the first and second portions of the conductive islands.

公开(公告)号：US20230387023A1

公开(公告)日：2023-11-30

申请号：US17826776

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; conductive contacts contacting the control gates, the conductive contacts having different lengths extending in a direction from one tier to another tier among the tiers; and a contact structure adjacent one of the conductive contacts. The contact structure includes a conductive core portion extending through the tiers and separated from the control gates, and a dielectric liner portion adjacent the conductive core portion. The dielectric liner portion includes a first dielectric material, a second dielectric material adjacent the first dielectric material, and a third dielectric material adjacent the second dielectric material.

公开(公告)号：US20230354601A1

公开(公告)日：2023-11-02

申请号：US17732286

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo

IPC: H01L27/11565

CPC classification number: H01L27/11565

Abstract: Methods, systems, and devices for divider and contact formation for memory cells are described. In some examples, a protective mask (e.g., a photoresist layer) may be formed over existing circuit structures above a substrate. Contact structures may be exposed when the protective mask is removed. In some examples, the protective mask may be removed using a dry etching operation. In some examples, one or more additional etching operations may be performed to expose (and subsequently fabricate) additional circuit structures.

公开(公告)号：US11742282B2

公开(公告)日：2023-08-29

申请号：US16988422

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John D. Hopkins ,  Shuangqiang Luo ,  Song Kai Tan ,  Jing Wai Fong ,  Anurag Jindal ,  Chieh Hsien Quek

IPC: H01L23/522 ,  H01L21/768 ,  H10B43/27 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877 ,  H10B43/27 ,  H01L23/53209 ,  H01L23/53266

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

公开(公告)号：US20230178488A1

公开(公告)日：2023-06-08

申请号：US17643061

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Xiao Li ,  Jivaan Kishore Jhothiraman ,  Mohadeseh Asadolahi Baboli

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/11556

Abstract: A microelectronic device comprises stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. The filled trench comprises a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions than the first protrusions. Memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20230157015A1

公开(公告)日：2023-05-18

申请号：US18152647

申请日：2023-01-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/528 ,  G11C5/025 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11637178B2

公开(公告)日：2023-04-25

申请号：US17078755

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Harsh Narendrakumar Jain

IPC: H01L29/06 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.