公开(公告)号：US5046048A

公开(公告)日：1991-09-03

申请号：US379280

申请日：1989-07-13

申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Junichi Miyamoto ,  Nobuaki Ohtsuka ,  Keniti Imamiya

发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Junichi Miyamoto ,  Nobuaki Ohtsuka ,  Keniti Imamiya

IPC分类号： G01R31/317 ,  G06F11/00 ,  G11C7/10 ,  G11C29/34 ,  G11C29/46

CPC分类号： G11C7/1057 ,  G01R31/31701 ,  G06F11/00 ,  G11C29/34 ,  G11C29/46 ,  G11C7/1051

摘要： A semiconductor integrated circuit having a test mode in addition to a normal mode, includes a mode detecting circuit for detecting a state of each mode and generating a mode signal, a prebuffer circuit for receiving the mode signal generated by the mode detecting circuit, amplifying an input signal by using an output driving capacity corresponding to the mode signal, and outputting the amplified signal, and an output buffer circuit for receiving an output from the prebuffer circuit and outputting data outside the integrated circuit.

公开(公告)号：US4916665A

公开(公告)日：1990-04-10

申请号：US610704

申请日：1984-05-16

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C11/417 ,  G11C16/28

CPC分类号： G11C16/28

摘要： A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

摘要翻译： 本发明的半导体存储器件具有多个浮动栅极存储单元。 检测器检测由解码器选择的存储在浮动栅极存储单元中的数据，并产生相应的检测信号。 负载电路放大检测信号。 放大的检测信号被提供给差分放大器。 差分放大器将放大的检测信号的电压与参考电压发生器的参考电压进行比较，并产生与浮动栅极存储器中的存储内容相对应的二进制信号。 负载电路是p沟道增强型MOS晶体管。 负载晶体管具有栅极和漏极，其连接到检​​测器和差分放大器之间的节点，并且还具有接收预定电压的源极和衬底。

公开(公告)号：US4897815A

公开(公告)日：1990-01-30

申请号：US96458

申请日：1987-09-15

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： H01L21/8247 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.

摘要翻译： 通过将其中以矩阵形式提供EPROM单元的存储单元阵列和写入电路划分成多个块来获得本发明的非易失性半导体存储器，通常连接存储单元阵列的每个块中的单元晶体管的源极， 并且通过相应的电阻分量将每个块的公共源连接到接地节点。

公开(公告)号：US4884241A

公开(公告)日：1989-11-28

申请号：US330040

申请日：1989-03-29

申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

IPC分类号： G11C11/41 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C16/28

摘要： A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

摘要翻译： 使用具有连接到位于主非易失性存储单元部分和非易失性虚设单元电路之间的第一和第二节点的输入端的差分放大器作为读出放大器。 在数据读出操作之前，第一和第二节点被预先充电到高电位电平。 存储单元部分和虚设单元电路被设置在电容平衡状态，从而可以高速地正确地读出数据。

公开(公告)号：US4860260A

公开(公告)日：1989-08-22

申请号：US59970

申请日：1987-06-09

申请人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

发明人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/781 ,  G11C29/24

摘要： A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

摘要翻译： 半导体存储器件包括主存储单元阵列，冗余存储单元阵列，用于接收地址信号的接合焊盘，用于根据行地址信号选择主存储单元阵列的行的行解码器，以及交换控制器 连接以接收地址信号，其可编程为响应于特定的地址信号而禁止行解码器的选择性操作来选择冗余存储单元阵列的行。 半导体存储器件还包括用于接收测试信号的接合焊盘。 交换控制器被连接以响应于测试信号接收用于禁止行解码器的选择性操作并选择冗余存储单元阵列的行的测试信号。

公开(公告)号：US4843594A

公开(公告)日：1989-06-27

申请号：US235780

申请日：1988-08-23

申请人： Sumio Tanaka ,  Shigeru Atsumi

发明人： Sumio Tanaka ,  Shigeru Atsumi

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/22 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C16/22

摘要： A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.

摘要翻译： 公开了一种非易失性半导体存储器件，包括连接到形成非易失性存储单元的存储单元晶体管的漏极的位线，第一p沟道MOS晶体管，第一晶体管的漏极和栅极连接到节点， 第一晶体管的源极连接到电源电位，串联连接在节点和参考电位之间的第二和第三n沟道MOS晶体管，第二晶体管的漏极和栅极互连，并且漏极和栅极 第三晶体管互连，以及第四n沟道MOS晶体管，用于控制位线的充电，第四晶体管的漏极 - 源极路径的一个端子连接到电源电位，另一个端子连接到位线 并且第四晶体管的栅极连接到节点。

公开(公告)号：US4825271A

公开(公告)日：1989-04-25

申请号：US50316

申请日：1987-05-15

申请人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L27/20 ,  H01L29/34

CPC分类号： H01L27/115 ,  Y10S257/915

摘要： Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.

摘要翻译： 公开了具有高访问速度和高可靠性的非易失性半导体存储器。 存储器包括沿一个方向延伸的源极扩散区域，与源极扩散区域平行布置的一对第一字线，使得源极扩散区域介于其间，设置成面对源极扩散区域的漏极扩散区域， 插入其间的第一字线，与漏极扩散区域电连接且布置成跨越第一字线的位线，形成在每个第一字线下方并位于源极扩散区域和漏极扩散区域之间的沟道区域，浮置 栅极电极以电浮置方式形成在沟道区域上方并且位于该对第一字线中的一个之上，以及第二字线，形成在源极区域之上并且位于第一字线对之间并电连接到该第一字线对之间。

公开(公告)号：US4694429A

公开(公告)日：1987-09-15

申请号：US802376

申请日：1985-11-27

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C16/24

摘要： There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and applying the clamped voltage to the bit line. The semiconductor memory device further comprises a bypass circuit connected between the bit line and a reference voltage, for bypassing from the bit line to the reference voltage an electric current the amount of which is substantially equal to that of a weak inversion current of the load MOS transistor flowing into said bit line.

摘要翻译： 公开了一种半导体存储器件，包括连接到位线的存储器单元和钳位电路，钳位电路包括连接在电源电压和位线之间的负载MOS晶体管，用于钳位电源电压并将钳位电压施加到 位线。 半导体存储器件还包括连接在位线和参考电压之间的旁路电路，用于从位线旁路到参考电压，该电流的量基本上等于负载MOS的弱反转电流的电流 流入所述位线的晶体管。

公开(公告)号：US4692902A

公开(公告)日：1987-09-08

申请号：US654215

申请日：1984-09-25

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/18 ,  G11C16/06 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C7/12 ,  G11C8/18

摘要： A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

摘要翻译： 一种半导体存储器件，其中差分放大器电路将存储信息的存储单元的位线的电位与连接有虚设单元的虚拟线的参考电位进行比较，并且检测存储在每个存储器中的信息 细胞。 半导体存储器件包括当提供芯片使能反转信号时将位线和虚拟线两者放电到低电位的电路。 因此，当提供芯片使能信号时，差分放大电路可以在位线完全充电之前检测位线电位和虚拟线电位之间的差异。 这使得可以产生芯片使能访问时间并实现更高速度的操作。

公开(公告)号：US4531202A

公开(公告)日：1985-07-23

申请号：US344049

申请日：1982-01-29

申请人： Shigeyoshi Watanabe ,  Sumio Tanaka

发明人： Shigeyoshi Watanabe ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/08 ,  G11C11/40

CPC分类号： G11C16/08

摘要： A semiconductor nonvolatile read only memory device has a voltage applying circuit which sets all word lines at ground potential in a stand-by mode and sets only a selected word line at a high level in an active mode. The word lines are connected to the gates of semiconductor nonvolatile memory transistors. Each of the memory transistors has the source (or drain) grounded and the drain (or source) connected to output lines. In a stand-by mode, the voltage applying circuit keeps all the word lines at ground potential. In an active mode, the voltage applying circuit applies a high level voltage only to the selected word line. The memory transistor connected to the selected word line produces data of "0" or "1" to the output line.

摘要翻译： 半导体非易失性只读存储器件具有电压施加电路，其以待机模式将所有字线设置为接地电位，并且在活动模式中仅将所选择的字线设置为高电平。 字线连接到半导体非易失性存储晶体管的栅极。 每个存储晶体管的源极（或漏极）接地，漏极（或源极）连接到输出线。 在待机模式下，电压施加电路使所有字线保持接地电位。 在有源模式下，电压施加电路仅对所选择的字线施加高电平电压。 连接到所选字线的存储晶体管对输出线产生“0”或“1”的数据。