公开(公告)号：US4956816A

公开(公告)日：1990-09-11

申请号：US358482

申请日：1989-05-30

申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

IPC分类号： G11C17/00 ,  G11C16/34 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C16/34 ,  G11C29/50 ,  G11C29/50016 ,  G06F2201/81 ,  G11C16/04

摘要： This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.

摘要翻译： 本发明提供一种具有第一节点和第二节点的非易失性半导体存储器，第二节点具有接地电位。 本发明包括多个具有漏极和阈值电位的非易失性存储单元，用于存储以预定的正常写入电压写入单元的数据。 多个位线，每个存储单元连接到一个位线，将数据传送到存储单元和从存储单元传送数据。 连接到位线的电路同时以正常写入电压测试所有位线的存储单元，以检测阈值电位的变化。

公开(公告)号：US4788663A

公开(公告)日：1988-11-29

申请号：US42877

申请日：1987-04-24

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C7/00 ,  H01L29/78

CPC分类号： G11C16/0441

摘要： Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

摘要翻译： EPROM中的每个存储单元包括两个存储单元晶体管，共享一个公共浮动栅极并具有两个分离的漏极，其中一个连接到读取位线，另一个连接到写入位线。 在该EPROM中，读取位线的读取存储单元晶体管的热电子注入速率低于写入位线的写入存储单元晶体管的热电子注入速率。 位线电压升压器连接到读位线。

公开(公告)号：US4879689A

公开(公告)日：1989-11-07

申请号：US30065

申请日：1987-03-25

申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobauki Otsuka

发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobauki Otsuka

IPC分类号： G11C17/00 ,  G11C16/08 ,  G11C16/22 ,  G11C16/32 ,  G11C29/00 ,  G11C29/46 ,  G11C29/52 ,  G11C29/56

CPC分类号： G11C29/52 ,  G11C16/08 ,  G11C16/225 ,  G11C16/32 ,  G11C29/46

摘要： A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal. The memory device further has a CE terminal for receiving a test-mode signal, an OE terminal for receiving first and second control signals, and a control circuit for detecting a test mode, thereby prohibiting the operation of the row decoder in response to the first control signal, and permitting the operation of the row decoder in response to the second control signal.

摘要翻译： 一种非易失性半导体存储器件，包括存储单元的矩阵阵列，用于驱动存储单元行的字线，用于从存储单元的列读取数据的位线，分别为这些位线提供的多个第一MOS晶体管，第二 MOS晶体管，其具有通过第一MOS晶体管耦合到位线的源极，耦合到VCC端子的漏极和连接以接收预定偏置电压的栅极;行解码器，用于根据行选择字线之一 地址信号，以及列解码器，用于根据列地址信号接通第一MOS晶体管中的一个。 存储装置还具有用于接收测试模式信号的＆amp; amp＆amp;＆amp; C端子，用于接收第一和第二控制信号的＆amp; upbar＆O端子，以及用于检测测试模式的控制电路，从而阻止行解码器响应于 第一控制信号，并且响应于第二控制信号允许行解码器的操作。

公开(公告)号：US4943962A

公开(公告)日：1990-07-24

申请号：US263752

申请日：1988-10-28

申请人： Keniti Imamiya ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Shinji Saito

发明人： Keniti Imamiya ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Shinji Saito

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

摘要翻译： 本发明的非易失性半导体存储器被构造成将输入数据锁存到数据锁存电路中，同时在芯片使能信号有效时控制位线负载晶体管的编程操作，并将页面编程电源电压设置为 编程电压，而输出使能信号保持不活动。 此外，当使输出使能信号有效或者将编程电源电压设置为与编程电压不同的电压时，复位数据锁存电路。 数据锁存电路可以通过预设的位组合来选择性地指定。

公开(公告)号：US4897815A

公开(公告)日：1990-01-30

申请号：US96458

申请日：1987-09-15

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： H01L21/8247 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.

摘要翻译： 通过将其中以矩阵形式提供EPROM单元的存储单元阵列和写入电路划分成多个块来获得本发明的非易失性半导体存储器，通常连接存储单元阵列的每个块中的单元晶体管的源极， 并且通过相应的电阻分量将每个块的公共源连接到接地节点。

公开(公告)号：US4884241A

公开(公告)日：1989-11-28

申请号：US330040

申请日：1989-03-29

申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Shinji Saito

IPC分类号： G11C11/41 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

CPC分类号： G11C16/28

摘要： A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

摘要翻译： 使用具有连接到位于主非易失性存储单元部分和非易失性虚设单元电路之间的第一和第二节点的输入端的差分放大器作为读出放大器。 在数据读出操作之前，第一和第二节点被预先充电到高电位电平。 存储单元部分和虚设单元电路被设置在电容平衡状态，从而可以高速地正确地读出数据。

公开(公告)号：US4860260A

公开(公告)日：1989-08-22

申请号：US59970

申请日：1987-06-09

申请人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

发明人： Shinji Saito ,  Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/781 ,  G11C29/24

摘要： A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

摘要翻译： 半导体存储器件包括主存储单元阵列，冗余存储单元阵列，用于接收地址信号的接合焊盘，用于根据行地址信号选择主存储单元阵列的行的行解码器，以及交换控制器 连接以接收地址信号，其可编程为响应于特定的地址信号而禁止行解码器的选择性操作来选择冗余存储单元阵列的行。 半导体存储器件还包括用于接收测试信号的接合焊盘。 交换控制器被连接以响应于测试信号接收用于禁止行解码器的选择性操作并选择冗余存储单元阵列的行的测试信号。

公开(公告)号：US4825271A

公开(公告)日：1989-04-25

申请号：US50316

申请日：1987-05-15

申请人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L27/20 ,  H01L29/34

CPC分类号： H01L27/115 ,  Y10S257/915

摘要： Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.

摘要翻译： 公开了具有高访问速度和高可靠性的非易失性半导体存储器。 存储器包括沿一个方向延伸的源极扩散区域，与源极扩散区域平行布置的一对第一字线，使得源极扩散区域介于其间，设置成面对源极扩散区域的漏极扩散区域， 插入其间的第一字线，与漏极扩散区域电连接且布置成跨越第一字线的位线，形成在每个第一字线下方并位于源极扩散区域和漏极扩散区域之间的沟道区域，浮置 栅极电极以电浮置方式形成在沟道区域上方并且位于该对第一字线中的一个之上，以及第二字线，形成在源极区域之上并且位于第一字线对之间并电连接到该第一字线对之间。

公开(公告)号：US4694429A

公开(公告)日：1987-09-15

申请号：US802376

申请日：1985-11-27

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

IPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C16/24

摘要： There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and applying the clamped voltage to the bit line. The semiconductor memory device further comprises a bypass circuit connected between the bit line and a reference voltage, for bypassing from the bit line to the reference voltage an electric current the amount of which is substantially equal to that of a weak inversion current of the load MOS transistor flowing into said bit line.

摘要翻译： 公开了一种半导体存储器件，包括连接到位线的存储器单元和钳位电路，钳位电路包括连接在电源电压和位线之间的负载MOS晶体管，用于钳位电源电压并将钳位电压施加到 位线。 半导体存储器件还包括连接在位线和参考电压之间的旁路电路，用于从位线旁路到参考电压，该电流的量基本上等于负载MOS的弱反转电流的电流 流入所述位线的晶体管。

公开(公告)号：US4692902A

公开(公告)日：1987-09-08

申请号：US654215

申请日：1984-09-25

申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/18 ,  G11C16/06 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C7/12 ,  G11C8/18

摘要： A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

摘要翻译： 一种半导体存储器件，其中差分放大器电路将存储信息的存储单元的位线的电位与连接有虚设单元的虚拟线的参考电位进行比较，并且检测存储在每个存储器中的信息 细胞。 半导体存储器件包括当提供芯片使能反转信号时将位线和虚拟线两者放电到低电位的电路。 因此，当提供芯片使能信号时，差分放大电路可以在位线完全充电之前检测位线电位和虚拟线电位之间的差异。 这使得可以产生芯片使能访问时间并实现更高速度的操作。