公开(公告)号：US11908839B2

公开(公告)日：2024-02-20

申请号：US17947752

申请日：2022-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

公开(公告)号：US11869591B2

公开(公告)日：2024-01-09

申请号：US18239117

申请日：2023-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: G11C16/04 ,  G11C11/408 ,  G11C16/08 ,  H10B80/00 ,  H10B43/35 ,  H10B12/00 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10

CPC classification number: G11C16/0483 ,  G11C11/4087 ,  G11C16/08 ,  H10B12/30 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

公开(公告)号：US11854646B1

公开(公告)日：2023-12-26

申请号：US18231235

申请日：2023-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C5/06 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L29/49 ,  H10B41/27 ,  G11C16/04 ,  H10B41/35 ,  H10B41/10

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L29/495 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

公开(公告)号：US20230395097A1

公开(公告)日：2023-12-07

申请号：US18231235

申请日：2023-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C5/06 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  G11C16/04 ,  H10B41/35 ,  H01L29/49

CPC classification number: G11C5/063 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  G11C16/0483 ,  H10B41/35 ,  H01L29/495

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

公开(公告)号：US20230329013A1

公开(公告)日：2023-10-12

申请号：US18206040

申请日：2023-06-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H10B12/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H10B12/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the plurality of first memory arrays includes a plurality of first DRAM (Dynamic Random Access Memory) cells, and where the plurality of second memory arrays includes a plurality of second DRAM (Dynamic Random Access Memory) cells.

公开(公告)号：US20230329011A1

公开(公告)日：2023-10-12

申请号：US18104299

申请日：2023-02-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/528 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L23/5286 ,  H01L25/50 ,  H01L23/481 ,  H01L24/08 ,  H01L2224/08145

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US11763864B2

公开(公告)日：2023-09-19

申请号：US17948225

申请日：2022-09-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C7/18 ,  G11C7/12 ,  G11C16/24 ,  G11C16/04 ,  H10B43/20

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C16/0466 ,  G11C16/24 ,  H10B43/20

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where a plurality of the channels are connected to a body pillar, and where the body pillar is at least temporary connected to a negative bias.

公开(公告)号：US11711928B2

公开(公告)日：2023-07-25

申请号：US18105856

申请日：2023-02-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/544 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

公开(公告)号：US20230041344A1

公开(公告)日：2023-02-09

申请号：US17947752

申请日：2022-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

公开(公告)号：US11482540B2

公开(公告)日：2022-10-25

申请号：US17681767

申请日：2022-02-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/1157

Abstract: A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.