公开(公告)号：US09406670B1

公开(公告)日：2016-08-02

申请号：US14514386

申请日：2014-10-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/528

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管通过包括铜或铝的至少一个金属层互连; 第二层包括第二晶体管，第一层由第二层覆盖，其中第二层包括直径小于200nm的多个通孔通孔，其中第二晶体管包括源极接触，源极接触包括 硅化物，其中硅化物的薄层电阻小于15欧姆/平方。

公开(公告)号：US20160218046A1

公开(公告)日：2016-07-28

申请号：US15089394

申请日：2016-04-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L23/34 ,  H01L23/522 ,  H01L27/06 ,  H03K3/037

CPC classification number: H01L27/0688 ,  H01L23/3677 ,  H01L23/5226 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，所述第二晶体管覆盖所述第一互连层，其中所述第一层包括第一时钟分配结构，其中所述第二层包括第二时钟分配结构，其中所述器件包括锁相环（“PLL” “）电路，其中第二时钟分配结构连接到锁相环（”PLL“）电路，并且其中第二晶体管与具有小于200nm对准误差的第一晶体管对准。

公开(公告)号：US09318408B2

公开(公告)日：2016-04-19

申请号：US14828517

申请日：2015-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H01L23/34 ,  H01L27/06 ,  H01L23/522 ,  H01L23/50

CPC classification number: H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分配结构，其中第二层包括第二时钟分配结构，其中第二时钟分配结构连接到第一层 具有多个贯通层通孔的时钟分配结构，并且其中第二晶体管与具有小于100nm对准误差的第一晶体管对准。

公开(公告)号：US08994404B1

公开(公告)日：2015-03-31

申请号：US13796930

申请日：2013-03-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H03K19/096

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 第二层，包括第二晶体管，第二晶体管覆盖第一层互连层; 所述第一层包括第一时钟分配结构，所述第一时钟分配结构包括第一时钟源，所述第二层包括第二时钟分配结构，所述第二时钟分配结构包括第二时钟源，并且所述第二时钟源正在馈送 第一时钟源。