公开(公告)号：US4316205A

公开(公告)日：1982-02-16

申请号：US119383

申请日：1980-02-07

申请人： Masakazu Aoki ,  Iwao Takemoto ,  Masaharu Kubo ,  Ryuichi Izawa

发明人： Masakazu Aoki ,  Iwao Takemoto ,  Masaharu Kubo ,  Ryuichi Izawa

IPC分类号： H01L27/146 ,  H01L31/113 ,  H04N5/335 ,  H04N5/374 ,  H01L27/14

CPC分类号： H01L31/1136 ,  H01L27/14643

摘要： In a solid-state imaging device having in one major surface region of a monolithic semiconductor body, photodiodes which are arrayed in two dimensions, vertical switching MOS transistors and horizontal switching MOS transistors which address the photodiodes, MOS transistors which constitute vertical and horizontal scanning circuits for turning "on" and "off" the switching MOS transistors, and MOS transistors which constitute other peripheral circuitry, the photodiodes being constructed of source regions of the vertical switching MOS transistors and the semiconductor body; a solid-state imaging device characterized in that among source and drain regions of the various MOS transistors, the source regions of the vertical switching MOS transistors are lower in the surface impurity concentration and deeper in the junction depth than the other source and drain regions.

摘要翻译： 在具有单片半导体主体的一个主表面区域的固态成像装置中，以二维排列的光电二极管，构成光电二极管的垂直开关MOS晶体管和水平开关MOS晶体管，构成垂直和水平扫描电路的MOS晶体管 为了使开关MOS晶体管“开”和“关”，构成其它外围电路的MOS晶体管，该光电二极管由垂直开关MOS晶体管和半导体本体的源极区构成; 一种固态成像装置，其特征在于，在各种MOS晶体管的源极和漏极区域中，垂直开关MOS晶体管的源极区域的表面杂质浓度较低，并且结深度比其他源极和漏极区域更深。

公开(公告)号：US4301477A

公开(公告)日：1981-11-17

申请号：US120115

申请日：1980-02-11

申请人： Iwao Takemoto ,  Masaharu Kubo ,  Shinya Ohba ,  Shuhei Tanaka ,  Masakazu Aoki

发明人： Iwao Takemoto ,  Masaharu Kubo ,  Shinya Ohba ,  Shuhei Tanaka ,  Masakazu Aoki

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/365 ,  H04N5/374 ,  H04N5/30 ,  H04N3/14

CPC分类号： H04N5/2173 ,  H01L27/14643 ,  H04N3/1568

摘要： In a solid-state imaging device comprising photodiodes arranged in a two-dimensional array, vertical and horizontal switching MOS transistors for selecting the photodiodes, vertical and horizontal scanning circuits for supplying scanning pulses to the gate electrodes of the vertical and horizontal switching MOS transistors respectively, a signal switching gate MOS transistor is connected between a signal output terminal and a horizontal signal output line connecting in common the horizontal switching MOS transistors.

摘要翻译： 在包括以二维阵列布置的光电二极管的固态成像装置中，用于选择光电二极管的垂直和水平切换MOS晶体管，分别向垂直和水平开关MOS晶体管的栅电极提供扫描脉冲的垂直和水平扫描电路 信号切换栅极MOS晶体管连接在水平开关MOS晶体管共同连接的信号输出端子和水平信号输出线之间。

公开(公告)号：US4199778A

公开(公告)日：1980-04-22

申请号：US843366

申请日：1977-10-19

申请人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

发明人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

IPC分类号： H01L21/763 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

CPC分类号： H01L21/32155 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002

摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

摘要翻译： 在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上 半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与 多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

公开(公告)号：US4015281A

公开(公告)日：1977-03-29

申请号：US121375

申请日：1971-03-05

申请人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

发明人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

IPC分类号： H01L21/765 ,  H01L27/088 ,  H01L29/51 ,  H01L27/02

CPC分类号： H01L29/511 ,  H01L21/765 ,  H01L27/0883

摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.

摘要翻译： 增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层 能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。