Transversal filter useable in echo canceler, decision feedback equalizer
applications for minimizing non-linear distortion in signals conveyed
over full duplex two-wire communication link
    61.
    发明授权
    Transversal filter useable in echo canceler, decision feedback equalizer applications for minimizing non-linear distortion in signals conveyed over full duplex two-wire communication link 失效
    用于回波消除器的横向滤波器,决策反馈均衡器应用,用于最小化通过全双工双线通信链路传送的信号中的非线性失真

    公开(公告)号:US5396517A

    公开(公告)日:1995-03-07

    申请号:US26491

    申请日:1993-03-04

    IPC分类号: H04B3/23 H03H7/30

    CPC分类号: H04B3/23

    摘要: The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.

    摘要翻译: 需要采用昂贵的精密元件来减少诸如回波消除器和判决反馈均衡器之类的噪声降低电路的信号处理路径中的非线性,这是通过横向滤波器来解决的,该滤波器能够有效跟踪系统组件中的非线性 这表现为引入信号传播路径的附加噪声。 这种非线性跟踪能力通过采用级联的加权系数和比例因子乘法级来实现。 第一组加权系数有效地修改横向滤波器延迟线中每个发射符号样本的内容,以产生与在数据调制方案中采用的相应数据符号相关联的各个“部分和”集合。 使用第二级联的“缩放”系数或因子来缩放部分和的集合中的所选择的一组。

    Methods for bonding semiconductor wafers
    62.
    发明授权
    Methods for bonding semiconductor wafers 有权
    接合半导体晶片的方法

    公开(公告)号:US09418830B2

    公开(公告)日:2016-08-16

    申请号:US14318063

    申请日:2014-06-27

    IPC分类号: H01L21/02 B81C1/00

    摘要: A method of bonding a cap wafer to a device wafer includes heating the device wafer and the cap wafer in the chamber, cooling the device wafer and the cap wafer in the chamber, pressurizing the chamber, introducing gas into the chamber while the chamber is pressurized to accelerate a rate of one of a group consisting of the heating and the cooling, and applying pressure to the device wafer and the cap wafer while a bond is formed between the device wafer and the cap wafer.

    摘要翻译: 将盖晶片接合到器件晶片的方法包括在腔室中加热器件晶片和盖晶片,冷却腔室中的器件晶片和盖晶片,对腔室加压,同时在腔室被加压的同时将气体引入腔室 以加速由加热和冷却组成的组中的一个的速率,以及在器件晶片和盖晶片之间形成结合时向器件晶片和盖晶片施加压力。

    Silicon nitride hardstop encapsulation layer for STI region
    63.
    发明授权
    Silicon nitride hardstop encapsulation layer for STI region 有权
    用于STI区域的氮化硅硬阻塞封装层

    公开(公告)号:US08030173B2

    公开(公告)日:2011-10-04

    申请号:US12475056

    申请日:2009-05-29

    IPC分类号: H01L21/76 H01L21/336

    摘要: A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the silicon nitride layer (96), and polishing and densifying the protective dielectric layer (97, 98) to thereby form a densified silicon nitride encapsulation layer (99) over the shallow trench isolation region (95).

    摘要翻译: 半导体工艺和装置通过形成氮化硅层(96)以覆盖浅沟槽隔离区(95),在氮化硅层(96)上沉积保护介电层(97,98)来提供封装的浅沟槽隔离区域, ,并抛光和致密化保护介电层(97,98),从而在浅沟槽隔离区域(95)上形成致密化的氮化硅封装层(99)。

    Silicon Nitride Hardstop Encapsulation Layer for STI Region
    64.
    发明申请
    Silicon Nitride Hardstop Encapsulation Layer for STI Region 有权
    用于STI区域的氮化硅硬质块封装层

    公开(公告)号:US20100304548A1

    公开(公告)日:2010-12-02

    申请号:US12475056

    申请日:2009-05-29

    IPC分类号: H01L21/762 H01L21/28

    摘要: A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the silicon nitride layer (96), and polishing and densifying the protective dielectric layer (97, 98) to thereby form a densified silicon nitride encapsulation layer (99) over the shallow trench isolation region (95).

    摘要翻译: 半导体工艺和装置通过形成氮化硅层(96)以覆盖浅沟槽隔离区(95),在氮化硅层(96)上沉积保护介电层(97,98)来提供封装的浅沟槽隔离区域, ,并抛光和致密化保护介电层(97,98),从而在浅沟槽隔离区域(95)上形成致密化的氮化硅封装层(99)。

    Process for control of polymer fines in a gas-phase polymerization
    66.
    发明授权
    Process for control of polymer fines in a gas-phase polymerization 失效
    在气相聚合中控制聚合物细粉的方法

    公开(公告)号:US07504464B2

    公开(公告)日:2009-03-17

    申请号:US10553689

    申请日:2004-04-07

    IPC分类号: C08F4/642

    摘要: A gas phase polymerization process comprising: (1) preparing a solution of a catalyst precursor comprising a mixture of magnesium and titanium compounds, an electron donor and a solvent; (2) adding a filler to the solution from step (1) to form a slurry; (3) spray drying the slurry from step (2) at a temperature of 100 to 140° C. to form a spray dried precursor, (4) slurring the spray dried precursor from step (3) in mineral oil, (5) partially or fully pre-activating the catalyst precursor by contacting the slurry of (4) with one or more Lewis Acids, and (6) transferring the partially or fully activated precursor from step (5) into a gas phase reactor in which an olefin polymerization reaction is in progress.

    摘要翻译: 一种气相聚合方法,包括:(1)制备包含镁和钛化合物,电子给体和溶剂的混合物的催化剂前体溶液; (2)向来自步骤(1)的溶液中加入填料以形成浆料; (3)在100〜140℃的温度下对来自步骤(2)的浆料进行喷雾干燥以形成喷雾干燥的前体,(4)将来自步骤(3)的喷雾干燥的前体在矿物油中sl浆,(5)部分 或通过使(4)的浆料与一种或多种路易斯酸接触来完全预活化催化剂前体,和(6)将来自步骤(5)的部分或完全活化的前体转移到气相反应器中,其中烯烃聚合反应 正在进行中

    Deep STI trench and SOI undercut enabling STI oxide stressor
    67.
    发明申请
    Deep STI trench and SOI undercut enabling STI oxide stressor 失效
    深STI沟槽和SOI底切使STI氧化应激反应

    公开(公告)号:US20080220617A1

    公开(公告)日:2008-09-11

    申请号:US11716058

    申请日:2007-03-07

    IPC分类号: H01L21/31

    摘要: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.

    摘要翻译: 提供了向晶体管的沟道区域施加应力的方法。 根据该方法,提供半导体层(307),其具有设置在其下方的电介质层(305)。 产生一个延伸穿过半导体层并进入电介质层的沟槽(319),沟槽用应力源材料(320)回填,从而形成沟槽隔离结构。 在与沟槽隔离结构相邻的半导体层中限定沟道区(326)。

    METHOD FOR STRAINING A SEMICONDUCTOR DEVICE
    68.
    发明申请
    METHOD FOR STRAINING A SEMICONDUCTOR DEVICE 审中-公开
    用于应变半导体器件的方法

    公开(公告)号:US20070298623A1

    公开(公告)日:2007-12-27

    申请号:US11426463

    申请日:2006-06-26

    IPC分类号: H01L21/31 H01L21/469

    摘要: A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain.

    摘要翻译: 应变半导体层通过覆盖的应力介电层实现。 电介质层中的应力通过辐射退火而增加。 辐射退火可以是通过使用激光束进行扫描或者同时向整个电介质层提供退火的闪光工具。 热量很强,最好是900-1400摄氏度,但持续时间不到10毫秒; 优选约1毫秒甚至更短。 辐射退火的结果也可用于激活源极/漏极。 因此,这种类型的辐射退火可导致应力的变化较大,源极/漏极的激活以及源极/漏极的扩展。

    Transistor structure with dual trench for optimized stress effect and method therefor
    69.
    发明授权
    Transistor structure with dual trench for optimized stress effect and method therefor 有权
    具有双沟槽的晶体管结构,用于优化应力效应及其方法

    公开(公告)号:US07276406B2

    公开(公告)日:2007-10-02

    申请号:US10977266

    申请日:2004-10-29

    IPC分类号: H01L21/8238

    摘要: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a or semiconductor-on-insulator substrate.

    摘要翻译: 用于形成半导体器件结构的一部分的方法包括提供具有半导体有源层,绝缘层和半导体衬底的绝缘体上半导体衬底。 第一隔离沟槽形成在半导体有源层内,并且应力源材料沉积在第一沟槽的底部上,其中应力源材料包括双重用途的膜。 第二隔离沟槽形成在半导体有源层内,其中第二隔离沟槽不存在第二沟槽底部上的应力源材料。 在第一和第二隔离沟槽中分别存在和不存在应力材料提供差分应力:(i)在半导体器件结构的一个或多个N型或P型器件中,(ii)对于一个或多个 的宽度方向或沟道方向取向,以及(iii)定制绝缘体上半导体衬底中的一个或多个的应力益处。

    Protective sleeve
    70.
    发明授权
    Protective sleeve 有权
    保护套

    公开(公告)号:US07119279B2

    公开(公告)日:2006-10-10

    申请号:US10704083

    申请日:2003-11-07

    IPC分类号: H02G3/04

    摘要: The present invention includes a protective sleeve assembly for cords having a longitudinal flexible sleeve for retaining the cords therein. The invention discloses various embodiments for obtaining a desired sleeve length. One such sleeve embodiment includes a pair of lengthwise fasteners affixed coterminously along its seam so that the sleeve and fasteners may be separated into a pair of sleeves. A method for protecting cords is provided as well.

    摘要翻译: 本发明包括用于帘线的保护套筒组件,其具有用于将绳索保持在其中的纵向柔性套筒。 本发明公开了用于获得期望的套筒长度的各种实施例。 一个这样的套筒实施例包括沿其接缝共同固定的一对纵向紧固件,使得套筒和紧固件可以分离成一对套筒。 还提供了一种用于保护电线的方法。