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    EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK
    62.
    发明申请
    EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK 有权
    有效的N-FACICE差分信令终止网络

    公开(公告)号：US20140254711A1

    公开(公告)日：2014-09-11

    申请号：US13832990

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

    IPC: H03H2/00 ,  H04B1/04

    CPC classification number: H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

    Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

    Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。

    C-PHY half-rate wire state encoder and decoder
    63.
    发明授权
    C-PHY half-rate wire state encoder and decoder 有权

    公开(公告)号：US11641294B2

    公开(公告)日：2023-05-02

    申请号：US17589083

    申请日：2022-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Ying Duan ,  Shih-Wei Chou

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    Termination for high-frequency transmission lines
    64.
    发明授权
    Termination for high-frequency transmission lines 有权

    公开(公告)号：US11431531B2

    公开(公告)日：2022-08-30

    申请号：US17197335

    申请日：2021-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Hyunjeong Park

    IPC: H04L25/02 ,  G06F13/40 ,  H04L25/03

    Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

    Three-input continuous-time amplifier and equalizer for multi-level signaling
    65.
    发明授权
    Three-input continuous-time amplifier and equalizer for multi-level signaling 有权

    公开(公告)号：US10389315B2

    公开(公告)日：2019-08-20

    申请号：US15912170

    申请日：2018-03-05

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Shih-Wei Chou ,  Ying Duan

    IPC: H03F3/217 ,  H03F1/02 ,  H03F3/68 ,  H03F3/45 ,  H03F3/21 ,  H04B1/06

    Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.

    Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols
    66.
    发明授权
    Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols 有权

    公开(公告)号：US10289600B2

    公开(公告)日：2019-05-14

    申请号：US15332756

    申请日：2016-10-24

    Applicant: QUALCOMM Incorporated

    Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

    IPC: G06F13/20 ,  G06F13/42 ,  H04L25/49 ,  H04L7/00

    Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

    Independent pair 3-phase eye sampling circuit
    67.
    发明授权
    Independent pair 3-phase eye sampling circuit 有权

    公开(公告)号：US10263766B1

    公开(公告)日：2019-04-16

    申请号：US16005231

    申请日：2018-06-11

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L7/00 ,  H04L7/02

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.

    N-phase signal transition alignment
    68.
    发明授权
    N-phase signal transition alignment 有权

    公开(公告)号：US10127167B2

    公开(公告)日：2018-11-13

    申请号：US15373645

    申请日：2016-12-09

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  George Alan Wiley

    IPC: H04L7/00 ,  G06F13/36 ,  G06F13/42 ,  H04L25/49 ,  G06F13/40 ,  H04L25/14

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

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