公开(公告)号：US20230298682A1

公开(公告)日：2023-09-21

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C7/1045 ,  G11C29/18 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11636231B2

公开(公告)日：2023-04-25

申请号：US16937907

申请日：2020-07-24

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Yanru Li ,  Dexter Tamio Chun

IPC: G06F21/79 ,  G06F11/07 ,  G06F12/14 ,  G06F21/31

Abstract: Various embodiments may include methods and systems for providing secure in-memory device access of a memory device by a system-on-a-chip (SOC). Various methods may include receiving a configuration message from the SOC for configuring a memory access control of the memory device, and configuring the memory access control based on the configuration message. Various embodiments may include receiving an access request message from the SOC requesting access to a memory base address and a memory access range of a memory cell array of the memory device, wherein the access request message includes a read/write operation. Various embodiments may include comparing the access request message with the configured memory access control to determine whether the access request message is allowable. Various embodiments may further include performing the read/write operation in response to determining that the access request message is allowable.

公开(公告)号：US11631450B2

公开(公告)日：2023-04-18

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US11372717B2

公开(公告)日：2022-06-28

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US11113074B2

公开(公告)日：2021-09-07

申请号：US16688978

申请日：2019-11-19

Applicant: QUALCOMM INCORPORATED

Inventor： Saurabh Gorecha ,  Naresh Kumar Sharma ,  Pravin Kumar ,  Dexter Tamio Chun ,  Christopher Kong Yee Chun

IPC: G06F9/4401 ,  H04L9/32 ,  G06F13/28 ,  H04L9/06 ,  G06F9/48

Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.

公开(公告)号：US10852809B2

公开(公告)日：2020-12-01

申请号：US16268634

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G06F1/3234 ,  G06F1/3225 ,  G06F13/42

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

公开(公告)号：US10224081B2

公开(公告)日：2019-03-05

申请号：US15849463

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F12/00 ,  G11C11/4076 ,  G06F11/10 ,  G11C11/406

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US10140223B2

公开(公告)日：2018-11-27

申请号：US15193423

申请日：2016-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun

IPC: G06F12/06 ,  H03M13/27 ,  G06F13/16 ,  G06F3/06 ,  G06F13/40

Abstract: A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.

公开(公告)号：US09947377B2

公开(公告)日：2018-04-17

申请号：US15622772

申请日：2017-06-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G06F12/02 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09928168B2

公开(公告)日：2018-03-27

申请号：US14993045

申请日：2016-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： Stephen Molloy ,  Dexter Tamio Chun

IPC: G06F12/06 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0866

CPC classification number: G06F12/0638 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0893 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/3042 ,  G06F2212/305

Abstract: Systems, methods, and computer programs are disclosed for providing non-volatile system memory with volatile memory program caching. One such method comprises storing an executable program in a non-volatile random access memory. In response to an initial launch of the executable program, the executable program is loaded from the non-volatile random access memory into a volatile memory cache for execution. In response to an initial suspension of the executable program, cache pages corresponding to the executable program are flushed into the non-volatile random access memory.