公开(公告)号：US10482929B2

公开(公告)日：2019-11-19

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C16/04 ,  G11C5/02 ,  G06N3/08 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/16 ,  G11C11/22 ,  G11C11/54 ,  G11C13/00

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

公开(公告)号：US10475889B1

公开(公告)日：2019-11-12

申请号：US15997991

申请日：2018-06-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L29/20 ,  H01L29/66 ,  H03F3/21 ,  H01L29/08 ,  H01L29/78

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.

公开(公告)号：US20190342106A1

公开(公告)日：2019-11-07

申请号：US15969043

申请日：2018-05-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Nicholas Ka Ming Stevens-Yu

IPC: H04L9/32 ,  G11C11/419 ,  G11C11/418 ,  G06F21/75

Abstract: Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word.

公开(公告)号：US10461164B2

公开(公告)日：2019-10-29

申请号：US15685877

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H01L29/423 ,  H01L29/66

Abstract: A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.

公开(公告)号：US10453774B1

公开(公告)日：2019-10-22

申请号：US16051528

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Bin Yang ,  Xia Li

IPC: H01L23/373 ,  H01L23/00 ,  H01L27/01 ,  H01L23/66 ,  H01L23/522

Abstract: Aspects generally relate to an integrated circuit including a glass substrate. On a surface of the glass substrate a thermally conductive insulating layer is formed. At least one metal layer is formed above the thermally conductive insulating layer, and a plurality of thermal bumps extend through the at least one metal layer and couple to the thermally conductive insulating layer to dissipate heat from the substrate.

公开(公告)号：US10446743B2

公开(公告)日：2019-10-15

申请号：US15868367

申请日：2018-01-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01L43/10

Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.

公开(公告)号：US10332590B2

公开(公告)日：2019-06-25

申请号：US15711110

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jianguo Yao

IPC: G11C11/419 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/10 ,  G11C11/412 ,  G11C11/56 ,  G11C8/16

Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.

公开(公告)号：US20190088310A1

公开(公告)日：2019-03-21

申请号：US15711110

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jianguo Yao

IPC: G11C11/419 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/419 ,  G11C7/1006 ,  G11C8/16 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/412 ,  G11C11/56

Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.

公开(公告)号：US10224368B2

公开(公告)日：2019-03-05

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10186514B1

公开(公告)日：2019-01-22

申请号：US15696630

申请日：2017-09-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Xia Li ,  Bin Yang

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/205 ,  H01L29/737 ,  H01L21/02 ,  H01L29/66 ,  H01L27/06 ,  G11C11/419 ,  H01L29/20 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate, first well layer formed over substrate from a III-V compound doped with a first type material, and second well layer formed over first well layer from a III-V compound doped with a second type material. Channel layer is formed over second well layer from a III-V compound doped with the first type material. Source and drain regions are formed over channel layer from a III-V compound doped with the first type material, and gate region is formed over channel layer. Bipolar junction transistors (BJTs) are formed such that a data value can be stored in second well layer. Collector tap electrode is configured to provide access to collector of each BJT for reading or writing data.