公开(公告)号：US20060112259A1

公开(公告)日：2006-05-25

申请号：US11323078

申请日：2005-12-30

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F9/30

CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

摘要翻译： 适用于特定于信号处理器（ASSP）的指令集体系结构（ISA）适用于数字信号处理应用。 采用ASSP实现的指令集架构适用于DSP算法结构。 ISA的指令字通常为20位，但可以扩展为40位，以控制串行或并行执行的两个指令。 ISA的所有DSP指令都是在一个周期内用一个指令执行两个操作的二进制DSP指令。 优选实施例中的DSP指令或操作包括乘法指令（MULT），加法指令（ADD），也称为极值指令的最小化/最大化指令（MIN / MAX）和无操作指令（NOP） 每个都具有相关联的操作代码（“操作码”）。 本发明通过指令集架构和应用专用信号处理器的硬件架构有效地执行DSP指令。

公开(公告)号：US06643768B2

公开(公告)日：2003-11-04

申请号：US10216044

申请日：2002-08-09

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F9302

CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

摘要： A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.

摘要翻译： 一种二进制数字信号处理（DSP）指令处理器，包括执行二进制DSP指令的主要操作的第一DSP功能块和第二DSP功能块，以执行二进制DSP指令的子操作，其中数据路径被选择性地配置为 执行二进制DSP指令的主要操作和子操作。 语音和数据通信系统具有耦合到分组化网络的第一网关和第二网关，每个网关具有包括二进制DSP指令处理器的网络接口。 一种具有信号处理器的应用专用信号处理器，具有第一DSP功能块，以执行二进制DSP指令的主操作和第二DSP功能块，以执行与第一DSP功能块和第二DSP功能的多路复用器的子操作 块以有选择地配置数据路径。

公开(公告)号：US06442672B1

公开(公告)日：2002-08-27

申请号：US09163741

申请日：1998-09-30

申请人： Kumar Ganapathy

发明人： Kumar Ganapathy

IPC分类号： G06F506

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3885 ,  G06F9/3897

摘要： The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

摘要翻译： 本发明是一种处理方法和处理器架构，其包含相同硅上的多个处理器，但是通过将处理单元静态地分配给处理器而不会产生固定的折中，而是动态地分配这样的处理单元，使得它们可以被有效地共享。 本发明可以提供与通过静态分配获得的功能相同的功能，并且可以在具有相同水平的性能的较低面积的单个芯片上实现。 优选架构使用可以被编程设置用于将通用控制从通用指令解码器传递到有限状态机的模式位。 优选架构还包括使用模式位作为其选择输入的多路复用器。

公开(公告)号：US09251899B2

公开(公告)日：2016-02-02

申请号：US12369733

申请日：2009-02-11

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G06F12/06 ,  G06F7/78 ,  G06F12/02 ,  G11C16/04 ,  G06F17/30

CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F17/30477 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

摘要： In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.

摘要翻译： 在本发明的一个实施例中，公开了一种在计算机系统中升级主存储器的方法。 该方法包括将多个二维存储器模块插入多个存储器模块插槽中，并将主存储器控制器耦合在一个或多个处理器与多个存储器模块之间。 二维存储器模块中的每一个包括多个存储器片中的存储器和分别耦合到多个存储器片中的存储器的多个从存储器控制器。 根据该升级方法还包括缓冲和转置用于一个或多个处理器的逐列格式的数据以及多个存储器片中的存储器的逐行格式。

公开(公告)号：US09251061B2

公开(公告)日：2016-02-02

申请号：US14016218

申请日：2013-09-02

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G06F12/02 ,  G11C5/04 ,  G11C29/00

CPC分类号： G06F12/0246 ,  G11C5/04 ,  G11C29/76

摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

公开(公告)号：US08874843B2

公开(公告)日：2014-10-28

申请号：US13750811

申请日：2013-01-25

申请人： Kenneth Alan Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

发明人： Kenneth Alan Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/205 ,  Y02D10/14

摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

摘要翻译： 公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片 。 所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。 第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

公开(公告)号：US20140075106A1

公开(公告)日：2014-03-13

申请号：US14016202

申请日：2013-09-02

申请人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

发明人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G06F13/1694 ,  G11C5/04 ,  Y02D10/14

摘要： A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

摘要翻译： 公开了一种计算机系统，其包括包括多个迹线的印刷电路板（PCB），至少一个处理器，其安装到PCB以耦合到多个迹线中的一些，异质存储器通道，包括耦合到存储器的多个插座 PCB的通道总线，以及耦合在所述至少一个处理器和所述异构存储器通道之间的存储器控​​制器。 异质存储器通道包括耦合到PCB的存储器通道总线的多个插座。 多个插槽被配置为接收多个不同类型的存储器模块。 存储器控制器可以是可编程异构存储器控制器，以灵活地适应存储器通道总线来控制对异质存储器通道中的每种不同类型的存储器模块的访问。

公开(公告)号：US20140071755A1

公开(公告)日：2014-03-13

申请号：US14016224

申请日：2013-09-03

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F17/30477 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

摘要翻译： 在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。 存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。 从存储器控制器从地址控制器接收存储器模块的存储器访问请求。 从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

公开(公告)号：US08555024B2

公开(公告)日：2013-10-08

申请号：US13443121

申请日：2012-04-10

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.

公开(公告)号：US08521967B1

公开(公告)日：2013-08-27

申请号：US12490941

申请日：2009-06-24

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

IPC分类号： G06F13/00 ,  G06F15/167

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F13/1694 ,  G06F2212/211

摘要： Network computing systems are disclosed including a shared memory cloud coupled to one or more processor complexes. The shared memory cloud has an interconnect network coupled to disk-read-only-memories (disk-ROMs) each including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations. The processor complexes read and write blocks of data from/to the disk-ROMs to provide disk-like access to the shared memory cloud. Each processor complex maps the addresses of one or more of the disk-ROMs into processor address spaces, and reads from random memory locations of one or more of the disk-ROMs to provide main memory-like access to the shared memory cloud. The network computing systems may further include a power controller coupled to the processor complexes. The power controller can keep the disk-ROMS powered on while it powers off inactive processor complexes.

摘要翻译： 公开了包括耦合到一个或多个处理器复合体的共享存储器云的网络计算系统。 共享存储器云具有耦合到磁盘只读存储器（磁盘 - ROM）的互连网络，每个磁盘 - 只读存储器（磁盘 - ROM）包括可访问连续存储器位置的块的读/写块的存储器阵列和访问随机存储器的随机读取存储器 位置。 处理器将读/写数据块从/到磁盘-ROM中，以便为共享内存云提供类似磁盘的访问。 每个处理器复合体将一个或多个磁盘ROM的地址映射到处理器地址空间中，并从一个或多个磁盘ROM的随机存储器位置读取以提供对共享存储器云的主存储器访问。 网络计算系统还可以包括耦合到处理器复合体的功率控制器。 电源控制器可以在关闭非活动处理器组合时关闭磁盘ROMS电源。