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    SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE
    61.
    发明申请
    SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE 有权
    半导体二极管及其制造方法

    公开(公告)号：US20150325567A1

    公开(公告)日：2015-11-12

    申请号：US14803365

    申请日：2015-07-20

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Gordon M. GRIVNA ,  Jefferson W. HALL ,  Mohammed Tanvir QUDDUS

    IPC: H01L27/02 ,  H01L29/872 ,  H01L29/10 ,  H01L29/423 ,  H01L27/06 ,  H01L29/78

    CPC classification number: H01L27/0255 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/8725

    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

    Abstract translation: 公开了一种二极管（200），其具有改进的效率，较小的外形尺寸和减小的反向偏置漏电流。 肖特基二极管（212）形成在台面区域（206）的侧壁（210）上。 台面区域（206）是肖特基二极管（212）的阴极。 通过台面区域（206）的电流路径具有横向和垂直电流路径。 二极管（200）还包括MOS结构（214），p型区（220），MOS结构（230）和p型区（232）。 具有p型区域（220）的MOS结构（214）在反向偏压条件下夹紧横向电流路径。 P型区域（220），MOS结构（230）和p型区域（232）各自在反向偏置条件下夹紧垂直电流路径。 MOS结构（214）和MOS结构（230）在正向偏置条件下降低横向和垂直电流通路的电阻。 台面区域（206）可以具有均匀或不均匀的掺杂浓度。

    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES
    64.
    发明公开
    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES 审中-公开

    公开(公告)号：US20230352525A1

    公开(公告)日：2023-11-02

    申请号：US18340650

    申请日：2023-06-23

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

    IPC: H01L29/06 ,  H01L25/07 ,  H01L29/20 ,  H01L21/762

    CPC classification number: H01L29/0649 ,  H01L25/071 ,  H01L29/2003 ,  H01L21/76224

    Abstract: In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

    SEMICONDUCTOR DEVICES WITH DISSIMLAR MATERIALS AND METHODS
    65.
    发明申请
    SEMICONDUCTOR DEVICES WITH DISSIMLAR MATERIALS AND METHODS 有权

    公开(公告)号：US20220093745A1

    公开(公告)日：2022-03-24

    申请号：US16948491

    申请日：2020-09-21

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. GRIVNA

    IPC: H01L29/165 ,  H01L49/02 ,  H01L29/06 ,  H01L21/285

    Abstract: A semiconductor device includes a substrate comprising a first material, a first major surface, and a second major surface opposite to the first major surface, the first material having a first coefficient of thermal expansion (CTE). A filled recessed structure having recesses extends into the substrate and has a pattern in a plan view. The recesses are spaced apart so that part of the substrate is interposed between each of the recesses, and a second material different than the first material is in the recesses. The second material has a second CTE. A structure is proximate to the first major surface over the filled recessed structure and has a third CTE. The third CTE and the second CTE are different than the first CTE. The filled recessed structure reduces stresses between the substrate and structure. In some examples, the structure comprises a MIM capacitor. In other examples, the structure comprises a heterojunction semiconductor material.

    STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE
    66.
    发明申请
    STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210296482A1

    公开(公告)日：2021-09-23

    申请号：US16948880

    申请日：2020-10-05

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. GRIVNA

    IPC: H01L29/78 ,  H01L29/06 ,  H01L23/48 ,  H01L21/78

    Abstract: A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE
    68.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE 审中-公开

    公开(公告)号：US20180323153A1

    公开(公告)日：2018-11-08

    申请号：US16035838

    申请日：2018-07-16

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. GRIVNA

    IPC: H01L23/544 ,  H01L21/78 ,  H01L23/58

    Abstract: A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

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