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    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    61.
    发明申请
    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20170085264A1

    公开(公告)日：2017-03-23

    申请号：US15279594

    申请日：2016-09-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Yuki OKAMOTO

    IPC: H03K19/00 ,  H03K19/177 ,  H03K19/0948

    CPC classification number: H03K19/0013 ,  H03K19/0948 ,  H03K19/17728 ,  H03K19/1776

    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    62.
    发明申请
    SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
    半导体器件，电子元件和电子器件

    公开(公告)号：US20160226490A1

    公开(公告)日：2016-08-04

    申请号：US15007350

    申请日：2016-01-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Yuki OKAMOTO

    IPC: H03K19/00 ,  H03K19/177 ,  H03K19/0948

    CPC classification number: H03K19/0013 ,  H03K19/0948 ,  H03K19/17728 ,  H03K19/1776

    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

    Abstract translation: 适用于低压驱动的半导体器件。 半导体器件包括第一晶体管，第二晶体管，电源线，电路和存储器电路。 第一个晶体管控制电路和电源线之间的电气连续性。 存储电路存储用于设置第一晶体管的栅极电位的数据。 第二晶体管控制存储电路的输出节点和第一晶体管的栅极之间的电连续性。 第二晶体管是具有超低截止电流的晶体管，例如氧化物半导体晶体管。 在用于操作电路的时段中，第一电位被输入到电源线并且第二晶体管被截止。 在用于更新第一晶体管的栅极电位的时段中，第二电位被输入到电源线。 第二个潜力高于第一个潜力。

    SEMICONDUCTOR DEVICE
    65.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150228324A1

    公开(公告)日：2015-08-13

    申请号：US14613554

    申请日：2015-02-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi AOKI ,  Munehiro KOZUMA

    IPC: G11C11/34

    CPC classification number: G11C11/34 ,  G06F17/5045 ,  G06F17/5054 ,  H03K19/177 ,  H03K19/1776

    Abstract: A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.

    Abstract translation: 提供了一种低功率半导体器件。 适用于多上下文可编程逻辑器件（PLD）的存储器件至少包括其数量与上下文数量相同的存储器单元。 存储单元的输出节点通过不同的路径晶体管电连接到配置存储器的输出节点。 包括晶体管和电容器的电路使路径晶体管的栅极电位高于高电位电位。 这防止由于路径晶体管的阈值电压而导致的配置存储器的输出节点的电位降低，而不增加功耗。

    SEMICONDUCTOR DEVICE
    66.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150213846A1

    公开(公告)日：2015-07-30

    申请号：US14602950

    申请日：2015-01-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takashi NAKAGAWA ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI

    IPC: G11C5/14 ,  G11C5/06

    CPC classification number: G11C5/148 ,  G11C11/24 ,  G11C14/0054

    Abstract: To provide a semiconductor device having a novel configuration, in which a malfunction and power consumption are reduced. A data holding circuit which includes a flipflop including first and second latch circuits and a shadow register including a nonvolatile memory portion; and a control signal generation circuit which generates a first control signal supplied to the first latch circuit and a second control signal supplied to the second latch circuit are included. The shadow register is a circuit which controls data saving or data restoring between the first and second latch circuits on the basis of a saving control signal or a restore control signal. The control signal generation circuit is a circuit which generates the first and second control signals at L level in a period during which data is saved or restored, on the basis of a clock signal, the saving control signal, and the restore control signal.

    Abstract translation: 为了提供具有新颖结构的半导体器件，其中故障和功耗降低。 一种数据保持电路，包括包括第一和第二锁存电路的触发器和包括非易失性存储器部分的影子寄存器; 以及产生提供给第一锁存电路的第一控制信号和提供给第二锁存电路的第二控制信号的控制信号产生电路。 影子寄存器是基于保存控制信号或恢复控制信号来控制第一和第二锁存电路之间的数据保存或数据恢复的电路。 控制信号生成电路是在时钟信号，保存控制信号以及恢复控制信号的基础上，在保存或恢复数据的期间，以L电平生成第一和第二控制信号的电路。

    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
    67.
    发明申请
    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 审中-公开
    半导体器件及其驱动方法

    公开(公告)号：US20150108556A1

    公开(公告)日：2015-04-23

    申请号：US14583363

    申请日：2014-12-26

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Munehiro KOZUMA ,  Takeshi AOKI

    IPC: H01L27/146

    CPC classification number: H01L27/14643 ,  G01J1/44 ,  H01L27/14609 ,  H04N5/378

    Abstract: A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor. In a period during which the second transistor and the third transistor are off, a voltage level of a voltage applied to a gate of the second transistor is set to be lower than a voltage level of a source of the second transistor and a voltage level of a drain of the second transistor, and a voltage level of a voltage applied to a gate of the third transistor is set to be lower than a voltage level of a source of the third transistor and a voltage level of a drain of the third transistor.

    Abstract translation: 半导体器件包括光电二极管，第一晶体管，第二晶体管和第三晶体管。 第二晶体管和第三晶体管具有保持积累在第一晶体管的栅极中的电荷的功能。 在第二晶体管和第三晶体管截止的期间，施加到第二晶体管的栅极的电压的电压电平被设定为低于第二晶体管的源极的电压电平， 第二晶体管的漏极和施加到第三晶体管的栅极的电压的电压电平被设置为低于第三晶体管的源极的电压电平和第三晶体管的漏极的电压电平。

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