公开(公告)号：US20150348981A1

公开(公告)日：2015-12-03

申请号：US14671606

申请日：2015-03-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L21/28 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  G11C16/14 ,  H01L29/66

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28008 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储器，包括：第一存储单元，包括浮栅晶体管和具有嵌入垂直控制栅极的选择晶体管，第二存储单元包括浮栅晶体管和 选择具有与第一存储单元的选择晶体管相同的控制栅极的晶体管，耦合到第一存储单元的浮置栅晶体管的第一位线和耦合到第二存储器的浮置栅极晶体管的第二位线 细胞。

公开(公告)号：US09012961B2

公开(公告)日：2015-04-21

申请号：US14148257

申请日：2014-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Hélène Dalle-Houilliez

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  G11C16/04

CPC classification number: H01L27/11556 ,  G11C16/0433 ,  H01L27/11524 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.

Abstract translation: 本公开涉及在半导体衬底中制造垂直栅极晶体管的方法，包括在衬底的深度中注入掺杂的隔离层，以形成晶体管的源极区域; 在衬底中形成垂直于沟槽隔离的平行沟槽隔离和第二沟槽，到达隔离层，并通过第一介电层与衬底隔离; 在所述衬底的表面和所述第二沟槽中沉积第一导电层; 蚀刻第一导电层以形成晶体管的垂直栅极，以及在垂直栅极的末端和衬底的边缘之间的垂直栅极连接焊盘，同时在每个连接焊盘和垂直栅极之间的第一导电层中保持连续区域 门; 以及在所述第二沟槽的每一侧上注入掺杂区域，以形成所述晶体管的漏极区域。

公开(公告)号：US20140246720A1

公开(公告)日：2014-09-04

申请号：US14194345

申请日：2014-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Abstract translation: 集成电路形成在半导体衬底上，并且包括沟槽导体和形成在衬底表面上的第一晶体管。 晶体管包括：晶体管栅极结构，在栅极结构的第一边缘和沟槽导体的上边缘之间的衬底中延伸的第一掺杂区域和形成在栅极结构的第一边缘上方的第一间隔区， 第一掺杂区域。 第一间隔物完全覆盖第一掺杂区域，并且硅化物存在于沟槽导体上，但不存在于第一掺杂区域的表面上。

公开(公告)号：US20140191291A1

公开(公告)日：2014-07-10

申请号：US14148257

申请日：2014-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Hélène Dalle-Houilliez

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  G11C16/0433 ,  H01L27/11524 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.

Abstract translation: 本公开涉及在半导体衬底中制造垂直栅极晶体管的方法，包括在衬底的深度中注入掺杂的隔离层，以形成晶体管的源极区域; 在衬底中形成垂直于沟槽隔离的平行沟槽隔离和第二沟槽，到达隔离层，并通过第一介电层与衬底隔离; 在所述衬底的表面和所述第二沟槽中沉积第一导电层; 蚀刻第一导电层以形成晶体管的垂直栅极，以及在垂直栅极的末端和衬底的边缘之间的垂直栅极连接焊盘，同时在每个连接焊盘和垂直栅极之间的第一导电层中保持连续区域 门; 以及在所述第二沟槽的每一侧上注入掺杂区域，以形成所述晶体管的漏极区域。

公开(公告)号：US20140097481A1

公开(公告)日：2014-04-10

申请号：US14043718

申请日：2013-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。