公开(公告)号：US11366507B2

公开(公告)日：2022-06-21

申请号：US17104460

申请日：2020-11-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C14/00 ,  G06F1/3234 ,  G11C5/14 ,  G11C16/30

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US11233055B2

公开(公告)日：2022-01-25

申请号：US16431778

申请日：2019-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L27/105 ,  H01L27/06 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US11056510B2

公开(公告)日：2021-07-06

申请号：US16927513

申请日：2020-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masayuki Sakakura

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US11037622B2

公开(公告)日：2021-06-15

申请号：US16759013

申请日：2018-11-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Kiyoshi Kato ,  Shuhei Maeda

IPC: G11C11/00 ,  G11C11/4094 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

公开(公告)号：US10797054B2

公开(公告)日：2020-10-06

申请号：US15292362

申请日：2016-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786 ,  G11C16/04

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US10553589B2

公开(公告)日：2020-02-04

申请号：US15995204

申请日：2018-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/11 ,  H01L27/105 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  H01L29/24 ,  H01L29/786 ,  G11C13/00 ,  H01L49/02

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US10382016B2

公开(公告)日：2019-08-13

申请号：US14669670

申请日：2015-03-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/037 ,  H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  G11C11/24 ,  G11C14/00 ,  H01L27/06 ,  H01L27/105 ,  H03K19/173

CPC classification number: H03K3/037 ,  G11C11/24 ,  G11C14/0054 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/7869 ,  H03K19/173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

公开(公告)号：US10319723B2

公开(公告)日：2019-06-11

申请号：US15722016

申请日：2017-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/06 ,  H01L27/12 ,  H01L27/105 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11521 ,  H01L27/11551

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US10297296B2

公开(公告)日：2019-05-21

申请号：US15695210

申请日：2017-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato

IPC: G11C14/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/56 ,  G11C5/14 ,  G11C11/412 ,  G11C11/419

Abstract: A storage device capable of performing power gating is provided. A memory cell of the storage device includes a bistable circuit, a first transistor, a second transistor, and a backup circuit. The first transistor and the second transistor are electrically connected to a first bit line and a second bit line, respectively. A precharge circuit that precharges the first bit line and the second bit line with different voltages is provided. The backup circuit includes a retention node, an input node, an output node, a third transistor, a fourth transistor, and a capacitor. The third transistor controls electrical continuity between the retention node and the input node. A gate of the fourth transistor and a terminal of the capacitor are electrically connected to the retention node. The input node is electrically connected to one of nodes Q and Qb of the bistable circuit, and the output node is electrically connected to the other of the nodes Q and Qb of the bistable circuit.

公开(公告)号：US10193563B2

公开(公告)日：2019-01-29

申请号：US15832114

申请日：2017-12-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yutaka Shionoiri ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46 ,  G11C27/02

Abstract: An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.