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公开(公告)号：US09905181B2
公开(公告)日：2018-02-27
申请号：US14908066
申请日：2015-12-29
Inventor： Peng Du
IPC: G09G3/36
CPC classification number: G09G3/3677 , G02F1/1345 , G09G2300/0426 , G09G2300/0439 , G09G2300/0809 , G09G2310/0205 , G09G2310/0251 , G09G2310/0286 , G09G2320/028 , G11C19/28
Abstract: The present disclosure discloses a scan driving circuit on an array substrate which includes a multi-stage cascade circuit, each stage of the cascade circuit inputs a clock signal corresponding to a current stage, and outputs an current stage scanning signal and a current stage cascade signal, different stages of the cascade circuit are connected with each other via a cascade signal; a plurality of cancellation circuits, each cancellation circuit is corresponding to one stage of the cascade circuit, the cancellation circuit corresponding to the current stage cascade circuit inputs a clock signal corresponding to an adjacent stage cascade circuit, and outputs a cancellation signal to offset a part of the current stage scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped. An array substrate is also disclosed in the present disclosure.
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公开(公告)号：US09887141B2
公开(公告)日：2018-02-06
申请号：US15491941
申请日：2017-04-19
Inventor： Peng Du , Cheng-hung Chen
IPC: H01L29/10 , H01L21/66 , H01L29/786 , H01L29/66 , H01L27/12
CPC classification number: H01L22/34 , H01L22/14 , H01L27/1244 , H01L27/127 , H01L29/66742 , H01L29/78609 , H01L29/78648 , H01L29/78696
Abstract: A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal. The gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.
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公开(公告)号：US09786241B2
公开(公告)日：2017-10-10
申请号：US14905876
申请日：2015-12-23
Inventor： Peng Du
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3696 , G09G2300/0408 , G09G2300/0809 , G09G2310/0286
Abstract: A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels.
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公开(公告)号：US20170153805A1
公开(公告)日：2017-06-01
申请号：US14785937
申请日：2015-07-20
Inventor： Peng Du
IPC: G06F3/0488
CPC classification number: G06F3/04883 , G06F3/0237 , G06F3/0488 , G06F9/3806 , G06F9/3832 , G06F9/3844 , G06F9/3846 , G06F9/3848 , G06F9/3861 , G06F19/702 , G06F19/704 , G06F2203/04104 , G06F2209/5019
Abstract: Disclosed is a method and system of gesture recognition in a touch display device, which is able to predetermine gesture inputs possibly to be made by a user prior to the completion of the user's touch input, and enable a display unit to display all possible similar gesture inputs so as to provide an instruction (or navigation guidance) for the user. Thus, when using a large-sized touch display device, the user does not have to perform touch operations widely throughout the screen of the display device, because the system can recognize the similar gesture inputs in advance, which renders it easier for the user to operate on the touch display device, thereby obtaining a better user experience.
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公开(公告)号：US09664969B2
公开(公告)日：2017-05-30
申请号：US14406699
申请日：2014-06-17
Inventor： Peng Du
IPC: H01L27/14 , G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/02 , H01L27/12 , H01L29/66
CPC classification number: G02F1/136286 , G02F1/1368 , G02F2001/136295 , G02F2201/40 , H01L21/0217 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/77 , H01L27/124 , H01L27/1288 , H01L29/66765
Abstract: The present disclosure discloses a TFT-LCD display panel based on an HSD structure, including: a sub-pixel unit array; a plurality of pairs of gate lines, with each pair being arranged between two adjacent rows of the sub-pixel units, wherein each gate line includes subsections arranged repeatedly and the subsection is consist of subsection portions with different widths, on the wider subsection portion of which a TFT element connected with a pixel electrode of the sub-pixel unit is placed; a plurality of data lines perpendicular to the gate lines, wherein two or more columns of sub-pixel units are arranged between two adjacent data lines. TFT elements of the present disclosure are placed on the gate lines other than the pixel region, which increases the open rate of the pixel region, and thus improves the penetration rate of the pixels.
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Patent Agency Ranking
公开(公告)号：US09658284B2
公开(公告)日：2017-05-23
申请号：US14423113
申请日：2015-01-06
IPC: G01R31/28 , H01L21/66 , H01L21/77 , H01L27/12 , H01L29/786
CPC classification number: G01R31/2884 , G01R31/28 , H01L21/77 , H01L22/14 , H01L22/32 , H01L27/12 , H01L29/78672
Abstract: The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.
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公开(公告)号：US20170139251A1
公开(公告)日：2017-05-18
申请号：US14778612
申请日：2015-08-24
IPC: G02F1/1333 , G02F1/1335 , G02F1/1343 , G06F3/041
CPC classification number: G02F1/13338 , G02F1/133512 , G02F1/134309 , G02F1/13439 , G02F2001/133742 , G02F2001/134318 , G02F2201/121 , G02F2201/122 , G02F2202/16 , G06F3/0412 , G06F3/044 , G06F2203/04103 , G06F2203/04107
Abstract: The present invention provides a VA type In-Cell touch control display panel structure, of which the color filter comprises a black matrix (12) of metal material and a common electrode layer (14). The black matrix (12) at least comprises a plurality of first black matrix vertical zones (121) which are separated along a vertical direction, and each independent first black matrix vertical zone (121) is employed to be a touch acceptance electrode (Rx(n)); the common electrode layer (14) at least comprises a plurality of first common electrode horizontal zones (141), which are separated along a horizontal direction, and each independent first common electrode horizontal zone (141) is employed to be a touch transmittance electrode (Tx(m)). The VA type In-Cell touch control display panel structure of the present invention has a simple manufacture flow which can effectively reduce the production cost and promote the yield of the touch control display panel.
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公开(公告)号：US09620536B2
公开(公告)日：2017-04-11
申请号：US14426464
申请日：2014-12-29
IPC: H01L27/12 , G02F1/1362 , G02F1/1333 , G02F1/1368 , H01L29/45 , H01L29/49 , H01L29/51 , H01L29/786
CPC classification number: H01L27/1288 , G02F1/133345 , G02F1/13338 , G02F1/1362 , G02F1/136209 , G02F1/136277 , G02F1/136286 , G02F1/1368 , G02F2001/133357 , G02F2001/136231 , G02F2202/104 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L29/51 , H01L29/518 , H01L29/78633 , H01L29/78675
Abstract: An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.
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公开(公告)号：US09568759B2
公开(公告)日：2017-02-14
申请号：US14650312
申请日：2015-02-13
IPC: G02F1/1333 , G02F1/1343 , G02F1/1335
CPC classification number: G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/133516 , G02F1/13439 , G02F2001/134318 , G02F2201/121 , G06F3/0412 , G06F3/044 , G06F2203/04103
Abstract: A manufacturing method of a touch display panel is disclosed and has steps of depositing a touch-control metal layer on ail inner side of a color-filler substrate and patterning the touch-control metal layer; depositing a black matrix layer on the inner side of the color-filter substrate and patterning the black matrix layer; depositing a color photoresist layer on the inner side of the color-filter substrate and patterning the color photoresist layer; depositing a common electrode layer on the inner side of the color-filter substrate and patterning the common electrode layer; and performing cell-assembling to assemble the color-filter substrate and an array substrate together.
Abstract translation: 公开了一种触摸显示面板的制造方法，并且具有将触控金属层沉积在彩色填充衬底的内侧并对触摸控制金属层进行图案化的步骤; 在所述滤色器基板的内侧上沉积黑矩阵层并对所述黑矩阵层进行构图; 在彩色滤光片基板的内侧上沉积彩色光致抗蚀剂层，并对彩色光致抗蚀剂层进行构图; 在所述滤色器基板的内侧上沉积公共电极层并对所述公共电极层进行构图; 并且进行电池组装以将滤色器基板和阵列基板组装在一起。
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公开(公告)号：US20160172387A1
公开(公告)日：2016-06-16
申请号：US14420901
申请日：2015-01-13
IPC: H01L27/12
CPC classification number: H01L27/1255 , H01L27/1222 , H01L27/1237 , H01L29/41733 , H01L29/78618 , H01L29/78633 , H01L29/78675
Abstract: An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate electrode line and a common electrode line, an insulation layer, a drain electrode and a source electrode, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. The bottom transparent conductive layer, the protection layer, and the top transparent conductive layer are sequentially stacked on the planarization layer. The patternized poly-silicon layer includes a first portion and a second portion. The drain electrode includes an extension section extending therefrom and opposite to the second portion.
Abstract translation: LTPS阵列基板包括多个LTPS薄膜晶体管和底部透明导电层，保护层和顶部透明导电层。 每个LTPS薄膜晶体管包括衬底，图案化的遮光层，缓冲层，图形化多晶硅层，栅极绝缘层，栅电极线和公共电极线，绝缘层，漏电极和 源电极和平坦化层，其形成为彼此顺序堆叠。 遮光层覆盖扫描线和源极/漏极。 底部透明导电层，保护层和顶部透明导电层依次层叠在平坦化层上。 图形化的多晶硅层包括第一部分和第二部分。 漏电极包括从其延伸并与第二部分相对的延伸部分。
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