公开(公告)号：US08184470B2

公开(公告)日：2012-05-22

申请号：US12668750

申请日：2008-06-25

申请人： Haruki Toda ,  Hiroto Nakai

发明人： Haruki Toda ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32

摘要： A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.

摘要翻译： 一种对电阻变化存储器件进行编程的方法包括：将程序电压脉冲施加到存储器单元以编程目标电阻值; 设置各个编程电压脉冲之间的热弛豫时间; 并且根据由先前的编程电压脉冲应用确定的当前单元的电阻值来控制每个编程电压脉冲的形状。

公开(公告)号：US08174864B2

公开(公告)日：2012-05-08

申请号：US12678159

申请日：2008-09-18

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/56 ,  G11C13/0033 ,  G11C13/004 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2213/72

摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.

公开(公告)号：US20120099370A1

公开(公告)日：2012-04-26

申请号：US13338950

申请日：2011-12-28

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C11/36 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.

摘要翻译： 存储器件包括衬底和堆叠在衬底上的多个单元阵列。 单元阵列具有耦合到存储器单元的第一端和耦合到另一端的字线的位线。 每个存储单元包括要设置在电阻值的可变电阻元件。 当所选择的位线被设置在某一电位时，顺序驱动耦合到不同存储器单元的字线，这些存储器单元被共同耦合到所选择的位线，使得不同的存储器单元以分时模式被访问。

公开(公告)号：US08102699B2

公开(公告)日：2012-01-24

申请号：US12966346

申请日：2010-12-13

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C7/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C11/36 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.

摘要翻译： 存储器件包括衬底和堆叠在衬底上的多个单元阵列。 单元阵列具有耦合到存储器单元的第一端和耦合到另一端的字线的位线。 每个存储单元包括要设置在电阻值的可变电阻元件。 当所选择的位线被设置在某一电位时，顺序驱动耦合到不同存储器单元的字线，这些存储器单元被共同耦合到所选择的位线，使得不同的存储器单元以分时模式被访问。

公开(公告)号：US08031508B2

公开(公告)日：2011-10-04

申请号：US12266879

申请日：2008-11-07

申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US08004873B2

公开(公告)日：2011-08-23

申请号：US12389606

申请日：2009-02-20

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C11/16 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.

摘要翻译： 一种电阻变化存储器件，包括具有第一布线，第二布线和存储单元的存储单元阵列，所述存储单元包括二极管和可变电阻元件，二极管的阳极位于第一布线侧，其中存储单元阵列为 在上电之后依次设置为以下三种状态：由第一和第二布线定义的等待状态被设置在第一电压; 待机状态由第一配线保持在第一电压而第二配线被设定在比第一电压高的第二电压; 并且由所选择的第一布线和所选择的第二布线定义的访问状态分别被设置为高于第一电压和第一电压的第三电压。

公开(公告)号：US08001448B2

公开(公告)日：2011-08-16

申请号：US11845999

申请日：2007-08-28

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： H03M13/00

CPC分类号： H03M13/152 ,  G06F11/1068 ,  H03M13/1575

摘要： A semiconductor memory device including an error detecting and correcting system, wherein the error detecting and correcting system includes a 3EC system configured to be able to detect and correct 3-bit errors, and wherein the 3EC system is configured to search errors in such a manner that 3-degree error searching equation is divided into a first part containing only unknown numbers and a second part calculative with syndromes via variable transformation by use of two or more parameters, and previously nominated solution indexes collected in a table and syndrome indexes are compared to each other.

摘要翻译： 一种包括错误检测和校正系统的半导体存储器件，其中所述错误检测和校正系统包括被配置为能够检测和校正3位错误的3EC系统，并且其中所述3EC系统被配置为以这种方式搜索错误 将3度误差搜索方程分为仅包含未知数的第一部分和通过使用两个或多个参数通过变量变换计算的第二部分，并将在表中收集的先前指定的解索引指数与综合征指数进行比较 彼此。

公开(公告)号：US07767993B2

公开(公告)日：2010-08-03

申请号：US11761758

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： H01L29/02

CPC分类号： G11C8/14 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147

摘要： A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of which serves as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.

摘要翻译： 一种电阻变化存储装置，包括基板，形成在基板上方彼此绝缘的第一和第二布线，以及设置在第一和第二布线之间的存储单元，其中存储单元包括：可变电阻元件，用于存储为 信息电阻值; 和与可变电阻元件串联连接的肖特基二极管。 可变电阻元件具有：由包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的复合化合物形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个用作写入或擦除模式的阳离子源，用于将阳离子供应到要容纳在其中的腔室位置的记录层。

公开(公告)号：US07719875B2

公开(公告)日：2010-05-18

申请号：US11761738

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/36 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/147 ,  H01L45/1675

摘要： A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value, and wherein the variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

摘要翻译： 一种电阻变化存储器件，包括：衬底; 单元阵列堆叠在其上，每个包括存储单元的矩阵布局; 写入电路，被配置为写入由两个相邻存储器单元构成的对单元; 以及读取电路，被配置为读取所述对单元的互补电阻值状态作为数据的一位，其中所述存储单元包括用于存储作为信息的电阻值的可变电阻元件，并且其中所述可变电阻元件具有由 由AxMyOz表示的第一复合化合物（其中“A”和“M”是彼此不同的阳离子元素;“O”氧;和0.5和nlE; x和nlE; 1.5,0.5和nlE; y和nlE; 2.5和1.5＆ ）和含有至少一个过渡元素和用于容纳阳离子离子的空腔部位的第二复合化合物。

公开(公告)号：US20100054019A1

公开(公告)日：2010-03-04

申请号：US12549948

申请日：2009-08-28

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C8/18

CPC分类号： G11C8/12 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.

摘要翻译： 一种电阻变化存储器件包括一个单元阵列，它具有层叠在其上的多个层，每个垫具有彼此相交的字线和位线以及布置在其交点处的电阻变化型存储单元，每个垫还具有其中 连接到参考单元的参考单元和参考位线，所述参考单元设置为一定电阻值的状态; 选择电路，被配置为选择单元阵列的每个矩阵中的字线，并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器，被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。