公开(公告)号：US20070187751A1

公开(公告)日：2007-08-16

申请号：US11355128

申请日：2006-02-14

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括具有低势垒高度的金属，用作肖特基源。 低阻挡高度的金属还可以包括PtSi或ErSi层。 在优选实施例中，低势垒高度的金属还包括ErSi层。 低势垒高度的金属还可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。 在优选实施例中，半导体功率器件构成非对称双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件。

公开(公告)号：US06277695B1

公开(公告)日：2001-08-21

申请号：US09293380

申请日：1999-04-16

申请人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

发明人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

IPC分类号： H01L21336

CPC分类号： H01L29/66719 ,  H01L29/66712

摘要： The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

摘要翻译： 通过在MOSFET的栅极上制造侧壁间隔来形成垂直平面DMOSFET中的源极和体区的金属接触。 以这种方式将金属接触自对准到栅极，DMOSFET中的每个电池的横向尺寸可以显着减小，而不会有接触和栅极之间短路的风险，并且电池的堆积密度可以 增加。 以这种方式，可以实现装置的导通电阻的显着降低。

公开(公告)号：US08907416B2

公开(公告)日：2014-12-09

申请号：US13780579

申请日：2013-02-28

申请人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

发明人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

摘要翻译： 公开了半导体器件和制造方法。 该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。 第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。 第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。 终端结构围绕第一和第二栅极流道和有源区域。 端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

公开(公告)号：US08536646B2

公开(公告)日：2013-09-17

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US08524558B2

公开(公告)日：2013-09-03

申请号：US13200882

申请日：2011-10-04

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08507362B2

公开(公告)日：2013-08-13

申请号：US13115097

申请日：2011-05-24

申请人： Tao Feng ,  Sung-Shan Tai

发明人： Tao Feng ,  Sung-Shan Tai

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/02035 ,  H01L21/02013 ,  H01L21/3043 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

公开(公告)号：US20130001699A1

公开(公告)日：2013-01-03

申请号：US13171475

申请日：2011-06-29

申请人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

发明人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

IPC分类号： H01L27/06 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L29/872

摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.

摘要翻译： 本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。 肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。 本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸 在两个沟槽之间的间距。

公开(公告)号：US08058687B2

公开(公告)日：2011-11-15

申请号：US11700688

申请日：2007-01-30

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08022482B2

公开(公告)日：2011-09-20

申请号：US11355128

申请日：2006-02-14

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/08 ,  H01L27/088 ,  H01L29/40 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括具有低势垒高度的金属，用作肖特基源。 低阻挡高度的金属还可以包括PtSi或ErSi层。 在优选实施例中，低势垒高度的金属还包括ErSi层。 低势垒高度的金属还可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。 在优选实施例中，半导体功率器件构成非对称双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件。

公开(公告)号：US20080179668A1

公开(公告)日：2008-07-31

申请号：US11700688

申请日：2007-01-30

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。