公开(公告)号：US08178923B2

公开(公告)日：2012-05-15

申请号：US12840283

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

摘要翻译： 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US08536646B2

公开(公告)日：2013-09-17

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US08362529B2

公开(公告)日：2013-01-29

申请号：US12784505

申请日：2010-05-21

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC分类号： H01L29/76

CPC分类号： H01L27/06 ,  H01L29/739

摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

摘要翻译： 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US20130001699A1

公开(公告)日：2013-01-03

申请号：US13171475

申请日：2011-06-29

申请人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

发明人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

IPC分类号： H01L27/06 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L29/872

摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.

摘要翻译： 本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。 肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。 本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸 在两个沟槽之间的间距。

公开(公告)号：US20110291183A1

公开(公告)日：2011-12-01

申请号：US12840283

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

摘要翻译： 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US20110215374A1

公开(公告)日：2011-09-08

申请号：US12784505

申请日：2010-05-21

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC分类号： H01L27/06 ,  H01L29/739 ,  H01L21/336

CPC分类号： H01L27/06 ,  H01L29/739

摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

摘要翻译： 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US07473598B2

公开(公告)日：2009-01-06

申请号：US11738511

申请日：2007-04-22

申请人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

发明人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L28/91

摘要： A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor.

摘要翻译： 形成堆叠电容器的方法包括在其上提供具有底层，BPSG层，USG层和顶层的衬底; 使用顶层作为硬掩模，并且将基板作为第一蚀刻停止层，以执行干蚀刻工艺以在底层，BPSG层和USG层中形成锥形沟槽; 去除顶层以执行选择性湿蚀刻工艺以部分去除BPSG层; 沉积多晶硅层并用牺牲层填充沟槽; 去除由牺牲层未掩蔽的多晶硅层; 使用底层作为第二蚀刻停止层进行湿蚀刻工艺以去除USG层和BPSG层; 进行静态干燥过程; 以及沉积介质层和导电材料以形成堆叠电容器。

公开(公告)号：US20080251827A1

公开(公告)日：2008-10-16

申请号：US11776558

申请日：2007-07-12

申请人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

发明人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  Y10S257/905 ,  Y10S257/906

摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

摘要翻译： 公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构 线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。 深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

公开(公告)号：US20130069143A1

公开(公告)日：2013-03-21

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  SUNG-SHAN TAI

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  SUNG-SHAN TAI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US07535045B2

公开(公告)日：2009-05-19

申请号：US11776558

申请日：2007-07-12

申请人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

发明人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  Y10S257/905 ,  Y10S257/906

摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

摘要翻译： 公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构 线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。 深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。