公开(公告)号：US20130248998A1

公开(公告)日：2013-09-26

申请号：US13619336

申请日：2012-09-14

申请人： Shinichiro Misu ,  Tsuyoshi Ota ,  Tatsuya Nishiwaki ,  Takeshi Uchihara ,  Yusuke Kawaguchi

发明人： Shinichiro Misu ,  Tsuyoshi Ota ,  Tatsuya Nishiwaki ,  Takeshi Uchihara ,  Yusuke Kawaguchi

IPC分类号： H01L29/78

CPC分类号： H01L29/7801 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/872

摘要： According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.

摘要翻译： 根据一个实施例，半导体器件包括漏极，源极，基极和漂移区，栅电极，栅绝缘膜，第一半导体区，漏电极和源电极。 漏区具有第一部分，第二部分具有沿垂直于第一部分的主表面的第一方向延伸的表面。 源极区域在与第二部分平行的第二方向上延伸，并且设置成与漏极区域间隔开。 栅极电极在第一方向和与第一方向和第二方向垂直的第三方向上延伸，并且在第三方向上穿过基极区域。 第一半导体区域设置在栅极绝缘膜和漏极区之间，并且具有比漂移区更低的杂质浓度。

公开(公告)号：US20070131967A1

公开(公告)日：2007-06-14

申请号：US11413115

申请日：2006-04-28

申请人： Yusuke Kawaguchi ,  Takeshi Meguro

发明人： Yusuke Kawaguchi ,  Takeshi Meguro

IPC分类号： H01L31/00

CPC分类号： H01L21/02008

摘要： A self-standing gallium nitride-based semiconductor single crystal substrate has a surface (Ga-face) mirror-polished, and a rear surface (N-face) having an arithmetic mean roughness Ra of 1 micrometer or more and 10 micrometers or less. A nitride semiconductor device is fabricated such that, before the gallium nitride-based semiconductor single crystal substrate is attached to a substrate holder of a vapor phase growth apparatus, the substrate is adjusted such that its rear surface (N-face) has a arithmetic mean roughness Ra to be in face-to-face contact with the substrate holder.

摘要翻译： 自立式氮化镓系半导体单晶基板具有镜面抛光的表面（Ga面）和具有1微米以上且10微米以下的算术平均粗糙度Ra的后表面（N面）。 制造氮化物半导体器件，使得在氮化镓基半导体单晶衬底附着到气相生长装置的衬底保持器之前，调节衬底，使得其背面（N面）具有算术平均值 粗糙度Ra与衬底保持器面对面接触。

公开(公告)号：US06614077B2

公开(公告)日：2003-09-02

申请号：US09796427

申请日：2001-03-02

申请人： Kazutoshi Nakamura ,  Akio Nakagawa ,  Yusuke Kawaguchi

发明人： Kazutoshi Nakamura ,  Akio Nakagawa ,  Yusuke Kawaguchi

IPC分类号： H01L2362

CPC分类号： H01L29/7393 ,  H01L29/7394 ,  H01L29/749 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an LDMOS, a p+-type anode layer is formed adjacent to an n+-type drain layer. The anode layer makes no contribution to an operation of the LDMOS at a rated voltage and generates holes at the time of ESD. The holes flow into the base layer through the active layer. Electrons flow from a source layer into the drain layer through the active layer. A parasitic thyristor of the LDMOS thus operates, with the result that a source-to-drain holding voltage can be lowered when a large current flows and the current distribution can be uniformed.

摘要翻译： 在LDMOS中，与n +型漏极层相邻形成p +型阳极层。 阳极层对额定电压下的LDMOS的操作没有贡献，并且在ESD时产生空穴。 孔通过活性层流入基层。 电子从源极层通过有源层流入漏极层。 因此，LDMOS的寄生晶闸管因此工作，结果是当大电流流动并且电流分布可以均匀化时，源极到漏极保持电压可以降低。

公开(公告)号：US06563193B1

公开(公告)日：2003-05-13

申请号：US09670548

申请日：2000-09-27

申请人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Tomoko Matsudai ,  Hirofumi Nagano ,  Akio Nakagawa

发明人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Tomoko Matsudai ,  Hirofumi Nagano ,  Akio Nakagawa

IPC分类号： H01L27082

CPC分类号： H01L29/7317 ,  H01L21/76286 ,  H01L21/763 ,  H01L29/735

摘要： A semiconductor device comprises a substrate the surface of which is formed of an insulation region, a high resistance active layer of a first conductivity type formed on the substrate, a first semiconductor region of the first conductivity type having an impurity concentration higher than that of the active layer and selectively formed on a surface of the active layer, an emitter region of the second conductivity type selectively formed on a surface of the semiconductor region, a collector region of the second conductivity type selectively formed on a surface of the active layer, and a base contact region of the first conductivity type selectively formed on a surface of the active layer in separation from the emitter region and the collector region, respectively. When an inversion layer is formed at an interface between the insulation region and the active layer due to the voltage of the substrate, the semiconductor region suppresses an emitter current flowing via the inversion layer thereby allowing the emitter current to flow on the surface side of the active layer.

摘要翻译： 半导体器件包括其表面由绝缘区域形成的衬底，形成在衬底上的第一导电类型的高电阻有源层，第一导电类型的第一半导体区域的杂质浓度高于 有源层，并且选择性地形成在有源层的表面上，选择性地形成在半导体区域的表面上的第二导电类型的发射极区域，选择性地形成在有源层的表面上的第二导电类型的集电极区域，以及 分别在与发射极区域和集电极区域分离的有源层的表面上分别形成有第一导电类型的基极接触区域。 当由于衬底的电压而在绝缘区域和有源层之间的界面处形成反型层时，半导体区域抑制通过反转层流动的发射极电流，从而允许发射极电流在 活动层

公开(公告)号：US06469346B1

公开(公告)日：2002-10-22

申请号：US09886204

申请日：2001-06-22

申请人： Yusuke Kawaguchi ,  Akio Nakagawa ,  Kozo Kinoshita

发明人： Yusuke Kawaguchi ,  Akio Nakagawa ,  Kozo Kinoshita

IPC分类号： H01L31119

CPC分类号： H01L29/0847 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is [Acm−1], the amount of charge of electrons is q[C], and the drift speed of carriers is &ugr;drift[cms−1], the dosage n2 of the second offset layer is given by n2≧ID/(q &ugr;drift) [cms−2].

摘要翻译： 高耐压半导体器件具有第一偏移层和第二偏移层，其剂量高于第一偏移层的掺杂层。 当门处于ON状态时，第一个偏移层用作resurf层。 当栅极处于截止状态时，第一偏移层中的电荷的一部分被流过具有低导通电阻的元件的漏极电流中和，然而，第二偏移层用作复现层。 当漏极电流为[Acm-1]时，电子的电荷量为q [C]，载流子的漂移速度为漂移[cms-1]，第二偏移层的剂量n2由 n2> = ID /（q＆ugr; drift）[cms-2]。

公开(公告)号：US06297534B1

公开(公告)日：2001-10-02

申请号：US09413811

申请日：1999-10-07

申请人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Akio Nakagawa

发明人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Akio Nakagawa

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7824

摘要： A first conductivity type active layer having high resistance is provided on an insulation region. A second conductivity type base layer is selectively formed on a surface of the first conductivity type active layer. A first conductivity type source layer is selectively formed on a surface of the second conductivity type base layer. A first conductivity type drain layer is selectively formed on a surface of the first conductivity type active layer. A gate electrode is formed facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. A plurality of first and second conductivity type semiconductor regions are formed between the second conductivity type base layer and the first conductivity type drain layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region. According to the present invention, low ON resistance and high withstand voltage are realized at the same time.

摘要翻译： 在绝缘区域上设置具有高电阻的第一导电型有源层。 在第一导电型有源层的表面上选择性地形成第二导电型基极层。 第一导电型源极层选择性地形成在第二导电型基极层的表面上。 第一导电型漏极层选择性地形成在第一导电型有源层的表面上。 栅极电极通过栅极绝缘膜形成在第一导电型源极层和第一导电型有源层之间的第二导电型基极层的表面区域。 在第二导电型基极层和第一导电型漏极层之间形成多个第一和第二导电型半导体区域。 每个第二导电类型半导体区域与第一导电类型半导体区域中的每一个交替布置。 漏极电流通过第一导电型半导体区域从第一导电型源极层流到第一导电型漏极层。 第二导电类型半导体区域的底部比第一导电型有源层和绝缘区域之间的界面浅。 根据本发明，同时实现低导通电阻和高耐受电压。

公开(公告)号：US6118149A

公开(公告)日：2000-09-12

申请号：US39389

申请日：1998-03-16

申请人： Akio Nakagawa ,  Yusuke Kawaguchi

发明人： Akio Nakagawa ,  Yusuke Kawaguchi

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/78645 ,  H01L29/78696 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/4175

摘要： The present invention discloses a semiconductor device which can be used as a switching element for portable appliances and realize a low breakdown voltage and a low ON resistance. More specifically, the semiconductor device is constructed in such a manner that a semiconductor layer is vertically or laterally sandwiched between gate electrodes through insulation films. In this polycrystalline semiconductor layer, a source region and a drain region are formed in both end portions thereof which contain an impurity at a concentration higher than the concentration in the middle portion thereof, and, in the middle portion, a channel region is formed, whereby carriers can be made to flow throughout the whole channel region.

摘要翻译： 本发明公开了一种可用作便携式电器的开关元件并实现低击穿电压和低导通电阻的半导体器件。 更具体地，半导体器件被构造成使得半导体层通过绝缘膜垂直或横向夹在栅电极之间。 在该多晶半导体层中，在其两端部形成有源区域和漏极区域，其两端部含有浓度高于其中间部分的浓度的杂质，在中间部分形成沟道区域， 由此可以使载流子流过整个通道区域。

公开(公告)号：US5932897A

公开(公告)日：1999-08-03

申请号：US172269

申请日：1998-10-14

申请人： Yusuke Kawaguchi ,  Akio Nakagawa ,  Kozo Kinoshita

发明人： Yusuke Kawaguchi ,  Akio Nakagawa ,  Kozo Kinoshita

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L27/108

CPC分类号： H01L29/7816 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/7835 ,  H01L29/42368

摘要： A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is �Acm.sup.-1 !, the amount of charge of electrons is q�C!, and the drift speed of carriers is .upsilon..sub.drift �cms.sup.-1 !, the dosage n.sub.2 of the second offset layer is given by n.sub.2 .gtoreq.I.sub.D /(q.upsilon..sub.drift)�cms.sup.-2 !.

摘要翻译： 高耐压半导体器件具有第一偏移层和第二偏移层，其剂量高于第一偏移层的掺杂层。 当门处于ON状态时，第一个偏移层用作resurf层。 当栅极处于截止状态时，第一偏移层中的电荷的一部分被流过具有低导通电阻的元件的漏极电流中和，然而，第二偏移层用作复现层。 当漏极电流为[Acm-1]时，电子的电荷量为q [C]，载流子的漂移速度为上漂移量[cms-1]，第二偏移层的剂量n2由n2 > / = ID /（q upsilon漂移）[cms-2]。

公开(公告)号：US08502309B2

公开(公告)日：2013-08-06

申请号：US12645072

申请日：2009-12-22

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US20120061747A1

公开(公告)日：2012-03-15

申请号：US13052917

申请日：2011-03-21

申请人： Takeshi UCHIHARA ,  Yusuke Kawaguchi ,  Keiko Kawamura ,  Hitoshi Shinohara ,  Yosefu Fujiki

发明人： Takeshi UCHIHARA ,  Yusuke Kawaguchi ,  Keiko Kawamura ,  Hitoshi Shinohara ,  Yosefu Fujiki

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7808

摘要： According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的漂移区域，第二导电类型的基极区域，第一导电类型的源极区域，沟槽形状的栅电极，第二导电类型的接触区域 导电类型，漏电极和源电极。 漂移区选择性地设置在从漏层的表面到漏层的内部的第一导电类型的漏极层中。 基极区域选择性地设置在漂移区域中，从漂移区域的表面到漂移区域的内部。 源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。 栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域，以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。 接触区选择性地设置在漂移区的表面上。 接触区域含有浓度高于碱性区域的杂质浓度的杂质。 漏电极连接到漏极层。 源电极连接到源极区域和接触区域。 接触区域从漏极层的侧面朝向漂移区域延伸，并且不接触漏极层。