Shift lever device
    61.
    发明授权
    Shift lever device 失效
    换档杆装置

    公开(公告)号:US5880422A

    公开(公告)日:1999-03-09

    申请号:US902080

    申请日:1997-07-29

    摘要: A shift lever 1 having an improved structure for holding a conductor wire 3 in position during assembly. The conductor wire 3 has one end 31 thereof disposed in a knob 2 of the shift lever 1. The conductor wire 3 is fitted with a terminal 41 to provide an electrical connection to a switch 4. The conductor wire 3 has a base portion 33 extending from a bent portion 32 formed in an intermediate portion toward the other end 34 of the conductor wire 3. The knob 2 has a conductor wire support hole 21 provided along the base portion 33 of the conductor wire 3. The positioning of the base portion 33 of the conductor wire 3 is performed by inserting a part 51 of a forming die 5 into the conductor wire support hole 21 when forming a flesh portion 23 of the shift lever 1. The shift lever 1 according to the invention holds the conductor wire 3 in a normal position for assembly when the conductor wire 3 is fitted with the terminal 41 of the switch 4 to provide an electrical connection.

    摘要翻译: 一种变速杆1,其具有改进的结构,用于在组装期间将导线3保持在适当的位置。 导线3的一端31设置在变速杆1的把手2中。导线3配有端子41,以提供与开关4的电连接。导线3具有延伸的基部33 从形成在中间部分的弯曲部分32朝向导体线3的另一端34.旋钮2具有沿着导线3的基部33设置的导线支撑孔21。基部33的定位 通过在形成变速杆1的肉部23时将成形模5的一部分51插入导体线支撑孔21中来进行。根据本发明的变速杆1将导线3保持在 当导线3装配有开关4的端子41以提供电连接时,用于组装的正常位置。

    Electrical connector
    62.
    发明授权
    Electrical connector 失效
    电连接器

    公开(公告)号:US5224876A

    公开(公告)日:1993-07-06

    申请号:US849690

    申请日:1992-03-12

    CPC分类号: H01R13/4367 H01R13/4223

    摘要: The object of the present invention is to provide an electrical connector in which terminals with wires having a diameter larger than another wire can be accommodated in the cavities of the connector without changing the size of the connector and without using a butt joint. The electrical connector according to the present invention includes a connector housing, a first terminal for connecting a first wire, the first terminal having an electrical contact portion at one end thereof, a conductor clamping portion at another end thereof, and intermediate portion, a second terminal for connecting a second wire having a diameter larger than that of the first wire, the second terminal having an electrical contact portion at one end thereof, a conductor clamping portion at another end thereof, and intermediate portion, the intermediate portion of the second terminal being formed to be longer than that of the first terminal, and a plurality of terminal accommodating cavities disposed in the connector housing for accommodating the first and second terminals, wherein each of the second terminals is accommodated so as to protrude form a rear end of the plurality of terminal accommodating cavities and at least one first terminal is disposed between the second terminals.

    摘要翻译: 本发明的目的是提供一种电连接器,其中具有大于另一导线的直径的导线的端子可以容纳在连接器的空腔中,而不改变连接器的尺寸并且不使用对接。 根据本发明的电连接器包括连接器壳体,用于连接第一线的第一端子,在其一端具有电接触部分的第一端子,在其另一端处的导体夹持部分和中间部分,第二端子 端子,用于连接直径大于第一线的直径的第二线,第二端在其一端具有电接触部分,在其另一端具有导体夹持部分和中间部分,第二端子的中间部分 被形成为比第一端子长,并且多个端子容纳腔设置在连接器壳体中,用于容纳第一和第二端子,其中每个第二端子被容纳以形成第二端子的后端 多个端子容纳腔和至少一个第一端子设置在第二端子之间 s。

    Digital synchronizing circuit
    65.
    发明授权
    Digital synchronizing circuit 失效
    数字同步电路

    公开(公告)号:US4759040A

    公开(公告)日:1988-07-19

    申请号:US945858

    申请日:1986-12-23

    摘要: CMI code has many features, but the interference on a transmission line resulted from radiant noise is an unavoidable problem. In the invention, WALSH 1 code is employed to solve the problem. Clock pulses having a frequency twice that of code on a transmission line in the WALSH 1 code are extracted. The extracted clock pulses consists of zero phase clock pulses and pi phase clock pulses, wherein the zero phase clock pulses are accurately extracted. An embodiment comprises an clock extraction circuit for extracting extracted clock pulses of 2f.sub.0 from a receive pulse train of frequency f.sub.0, a latch circuit for latching the receive pulse train with the extracted clock pulses, a frame synchronizing circuit for obtaining frame pulses synchronized with the extracted clock pulses from the latched output pulses, a zero phase separation circuit for obtaining zero phase clock pulses from the extracted clock pulses and the frame pulses, and a regenerative discrimination circuit for obtaining a regenerated pulse train from the zero phase clock pulses and the latched output pulses. The regenerated pulse train has the same pattern as that of the original code from which the receive pulse train is converted by the WALSH 1 code.

    摘要翻译: CMI代码具有很多功能,但由辐射噪声引起的传输线上的干扰是不可避免的问题。 在本发明中,采用WALSH 1代码来解决问题。 提取具有WALSH 1代码中的传输线上的代码的频率的两倍的时钟脉冲。 所提取的时钟脉冲由零相位时钟脉冲和pi相位时钟脉冲组成,其中准相位提取零相位时钟脉冲。 实施例包括:时钟提取电路,用于从频率f0的接收脉冲串中提取2f0的提取时钟脉冲;锁存电路,用于以提取的时钟脉冲锁存接收脉冲串;帧同步电路,用于获得与所提取的帧同步的帧脉冲 来自锁存的输出脉冲的时钟脉冲,用于从提取的时钟脉冲和帧脉冲获得零相位时钟脉冲的零相位分离电路,以及用于从零相位时钟脉冲和锁存输出获得再生脉冲串的再生鉴别电路 脉冲。 再生脉冲串具有与通过WALSH 1码转换接收脉冲串的原始码相同的图案。

    Data processing device utilizing way selection of set associative cache memory based on select data such as parity data
    66.
    发明授权
    Data processing device utilizing way selection of set associative cache memory based on select data such as parity data 有权
    基于诸如奇偶校验数据的选择数据,利用组合关联高速缓冲存储器的方式选择的数据处理装置

    公开(公告)号:US09495299B2

    公开(公告)日:2016-11-15

    申请号:US14367925

    申请日:2011-12-26

    摘要: Part of a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read. Further, when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data. For select data used for selecting a way, e.g. parity data in connection with tag address information is used. A way to read a cache tag from is selected based on a value of parity data and further, the way of a cache entry to perform cache fill on is selected.

    摘要翻译: 从根据作为地址信息的一部分的标签地址信息创建的选择数据的值的方式中选择多种方式的一部分,并且读取高速缓存标签。 此外,当执行高速缓冲存储器填充时,高速缓存存储器根据选择数据的值对从部分方式中选择的高速缓存条目执行高速缓存填充。 对于用于选择方法的选择数据,例如 使用与标签地址信息相关的奇偶校验数据。 基于奇偶校验数据的值来选择读取缓存标签的方式,并且进一步选择执行高速缓存填充的高速缓存条目的方式。

    FUEL CELL MODULE
    67.
    发明申请
    FUEL CELL MODULE 审中-公开
    燃料电池模块

    公开(公告)号:US20130236803A1

    公开(公告)日:2013-09-12

    申请号:US13202925

    申请日:2010-12-02

    IPC分类号: H01M8/02

    摘要: A fuel cell module which is capable of easily securing an adequate sealing function even when the unit cell is made thinner. The fuel cell module includes a stacked body which includes: a stacked structure including: an electrolyte layer, and a pair of electrodes provided to sandwich the electrolyte layer; and a pair of separators disposed to sandwich the stacked structure, the separators being arranged at least one end of the stacked body in the stacking direction, the separators which are arranged at the end of the stacked body having a groove which is capable of receiving a sealing member in a face which does not oppose to the stacked structure, and the at least one groove being a deep groove of which depth is larger than the thickness of the separator having the groove.

    摘要翻译: 一种燃料电池模块,即使当单元电池变薄时,也能够容易地确保足够的密封功能。 燃料电池模块包括层叠体,其包括:层叠结构,包括:电解质层和设置成夹持电解质层的一对电极; 以及一对分隔件,其被设置为夹着所述堆叠结构,所述隔板在层叠方向上布置在所述层叠体的至少一个端部,所述隔板布置在所述层叠体的端部,所述隔板具有能够接收 密封构件在不与堆叠结构相对的面中,并且所述至少一个凹槽是深度大于具有凹槽的隔膜的厚度的深槽。

    Multiprocessor system and method of synchronization for multiprocessor system
    69.
    发明授权
    Multiprocessor system and method of synchronization for multiprocessor system 有权
    多处理器系统的多处理器系统和同步方法

    公开(公告)号:US08108660B2

    公开(公告)日:2012-01-31

    申请号:US12358233

    申请日:2009-01-22

    IPC分类号: G06F1/04

    CPC分类号: G06F15/16

    摘要: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

    摘要翻译: 每个处理器都有一个屏障写入寄存器和一个屏障读取寄存器。 每个屏障写入寄存器通过专用接线块连接到每个屏障读取寄存器。 例如,处理器的1位屏障写入寄存器经由布线块连接到处理器中包含的每个8位屏障读取寄存器的第一位,而另一个处理器的1位屏障写入寄存器是 通过接线块连接到处理器中包含的每个8位屏障读取寄存器的第二位。 例如,处理器将信息写入其自己的屏障写入寄存器,从而通知其他处理器的同步待机并读取其自己的障碍读取寄存器,从而识别其他处理器是否处于同步待机状态。 因此,沿着屏障同步处理不需要特殊的专用指令,并且可以高速进行处理。

    Terminal emulation program, storage medium, load test method, load test apparatus, and load test system
    70.
    发明授权
    Terminal emulation program, storage medium, load test method, load test apparatus, and load test system 有权
    终端仿真程序,存储介质,负载测试方法,负载测试仪器和负载测试系统

    公开(公告)号:US07966390B2

    公开(公告)日:2011-06-21

    申请号:US10898359

    申请日:2004-07-26

    IPC分类号: G06F15/173

    CPC分类号: H04L41/22

    摘要: A load test apparatus includes a computer which is implemented with an operating system having a window management function, and can be connected to a network device to be tested through an information network, and a terminal emulation program used to direct a computer to perform a first function for providing an execution environment in an MDI system of an application in a plurality of virtual terminals in a first window, and a second function capable of generating a plurality of second windows which cannot be discriminated by the window management function in the first window by managing independently from the operating system the second window generated in the first window. The terminal emulation program is executed by the computer to access to the network device from the plurality of virtual terminals, thereby conducting a load test.

    摘要翻译: 负载测试装置包括:具有窗口管理功能的操作系统实现的计算机,并且可以通过信息网络连接到要测试的网络设备;以及终端仿真程序,用于引导计算机执行第一 用于在第一窗口中的多个虚拟终端中的应用的MDI系统中提供执行环境的功能,以及能够生成不能被第一窗口中的窗口管理功能区分的多个第二窗口的第二功能 独立于操作系统管理第一个窗口中生成的第二个窗口。 终端仿真程序由计算机执行,以从多个虚拟终端接入网络设备,从而进行负载测试。