公开(公告)号：US06958291B2

公开(公告)日：2005-10-25

申请号：US10654757

申请日：2003-09-04

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76846

摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

公开(公告)号：US06706577B1

公开(公告)日：2004-03-16

申请号：US09298879

申请日：1999-04-26

申请人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L218238

CPC分类号： H01L21/823857 ,  H01L27/10894

摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.

摘要翻译： 描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。 提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将 形成。 半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。 低电压有源区域用掩模覆盖。 半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。 去除面具。 一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极 集成电路。

公开(公告)号：US6165052A

公开(公告)日：2000-12-26

申请号：US192518

申请日：1998-11-16

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： B24B37/04 ,  B24B49/16 ,  H01L21/306 ,  B24B1/00

CPC分类号： B24B37/013 ,  B24B37/04 ,  B24B37/042 ,  B24B49/16 ,  H01L21/30625

摘要： A method to planarize the surface of a semiconductor substrate having shallow trench isolation (STI) reduces erosion of a silicon nitride planarization stop layer, reduces dishing of large areas of the shallow trench isolation, and prevents under polishing of the surface of the semiconductor substrate that will leave portions of the silicon dioxide that fills the shallow trenches covering the silicon nitride planarization stop exposed, is described. The method to planarize the surface of a semiconductor substrate having shallow trenches begins by chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize the semiconductor substrate. Polishing at a first product of platen pressure and platen speed will cause a high rate of material removal with low selectivity to increase production throughput. The silicon nitride stop layer will be examined to determine an end point exposure of the silicon nitride stop layer. When the end point exposure of the silicon nitride stop layer is reached, chemical/mechanical planarization polishing at a low product of platen pressure and platen speed is started to planarize the semiconductor substrate of slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion. The method further has the step of buffing the surface of the semiconductor substrate to remove any residue from the chemical/mechanical planarization polishing and to remove any microscratches from the surface of the semiconductor substrate.

摘要翻译： 平坦化具有浅沟槽隔离（STI）的半导体衬底的表面的方法减少了氮化硅平坦化停止层的侵蚀，减少了大面积浅沟槽隔离的凹陷，并且防止在半导体衬底的表面的抛光 将描述填充覆盖氮化硅平坦化止挡露出的浅沟槽的二氧化硅部分。 平面化具有浅沟槽的半导体衬底的表面的方法开始于在压板压力和压板速度的第一乘积上的化学/机械平面化抛光，以使半导体衬底平坦化。 在压板压力和压板速度的第一个产品上进行抛光将导致高选择性的材料去除率，从而提高生产量。 将检查氮化硅阻挡层以确定氮化硅阻挡层的端点暴露。 当达到氮化硅终止层的终点曝光时，开始以压板压力和压板速度的低乘积进行化学/机械平面化抛光，以平缓化缓慢过抛光的半导体衬底，以控制浅层的沟槽氧化物的厚度 沟槽隔离以减少凹陷和最小化侵蚀。 该方法还具有抛光半导体衬底的表面以从化学/机械平面化抛光中除去任何残余物并从半导体衬底的表面去除任何微细凹凸的步骤。

公开(公告)号：US6114253A

公开(公告)日：2000-09-05

申请号：US268542

申请日：1999-03-15

申请人： Syun-Ming Jang ,  Ming-Hsin Huang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ming-Hsin Huang ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31055

摘要： A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.

摘要翻译： 描述了用于去除用于蚀刻低k有机聚合物介电层中的通孔的残余氧化硅硬掩模的工艺。 当用于在高密度等离子体蚀刻机中在氧气/惰性气体等离子体中蚀刻有机聚合物层时，通过沿着图案边缘开发角度方面或刻面，硬掩模劣化。 此外，在有机聚合物蚀刻期间硬掩模的劣化导致表面平面度的显着降低，这会在将硬掩模留在原位时在其上形成第二金属层时导致通孔到通孔短路。 在通过等离子体蚀刻的通孔蚀刻之后立即选择性地去除残余硬掩模，该等离子体蚀刻恢复表面平面度并且经由边缘面移除。 等离子体蚀刻具有高的氧化物对有机聚合物的选择性，使得表面不规则性不会转移到聚合物表面，并且通孔底部的暴露的金属表面也是无损的。

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US5871886A

公开(公告)日：1999-02-16

申请号：US764288

申请日：1996-12-12

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： G03F7/09 ,  H01L21/027 ,  G03F7/00

CPC分类号： H01L21/0276 ,  G03F7/091

摘要： A method of patterning a layer of reflective material, such as a layer of conductor metal, using a layer of antireflection coating material sandwiched between two layers of photoresist. A first layer of photoresist is formed on an integrated circuit wafer and provides a planar surface for subsequent layers of material. A layer of antireflection coating material is formed on the layer of first photoresist and a layer of second photoresist is formed on the layer of antireflection coating material. The layer of second photoresist is selectively exposed and developed. The layer of antireflection coating material is patterned using dry etching and the patterned layer of second photoresist as a mask. The layer of first photoresist is then patterned using dry etching and the patterned layer of antireflection coating material as a mask. The layer of reflecting material is then patterned using dry etching and the patterned layer of first photoresist as a mask. The patterned layer of first photoresist is then removed.

摘要翻译： 使用夹在两层光致抗蚀剂之间的抗反射涂层层来图案化反射材料层（例如导体金属层）的方法。 在集成电路晶片上形成第一层光致抗蚀剂，并为随后的材料层提供平面。 在第一光致抗蚀剂层上形成防反射涂层，在抗反射涂层层上形成第二光致抗蚀剂层。 选择性地曝光和显影第二光致抗蚀剂层。 使用干蚀刻和第二光致抗蚀剂的图案化层作为掩模来图案化抗反射涂层材料层。 然后使用干蚀刻和防反射涂层材料的图案化层作为掩模来将第一光致抗蚀剂层图案化。 然后使用干蚀刻和第一光致抗蚀剂的图案化层作为掩模来图案化反射材料层。 然后去除第一光致抗蚀剂的图案化层。

公开(公告)号：US5747380A

公开(公告)日：1998-05-05

申请号：US606833

申请日：1996-02-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L21/44

CPC分类号： B24B37/013 ,  H01L21/768 ,  H01L22/26 ,  Y10S438/926

摘要： A method for improving the end-point detection for contact and via etching is disclosed. The disclosure describes the deliberate addition of dummy patterns in the form of contact and via holes to the regular functional holes in order to increase the amount of etchable surface area. It is shown that, one can then take advantage of the marked change in the composition of the etchant gas species that occurs as soon as what was once a large exposed area has now been consumed through the etching process. This then gives a strong and robust signal for the end of the etching process. This in turn results in better controlled and more reliable product. It is also indicated that with the full uniform pattern of the via layers now possible, the chemical/mechanical polishing process becomes much less pattern sensitive.

摘要翻译： 公开了一种用于改善接触和通孔蚀刻的端点检测的方法。 本公开描述了将接触孔和通孔形式的虚拟图案有意添加到常规功能孔，以增加可蚀刻表面积的量。 可以看出，一旦现在通过蚀刻工艺消耗了大的暴露区域，就可以利用所发生的蚀刻剂气体种类的组成的明显变化。 这就为腐蚀过程的结束提供了一个强大而鲁棒的信号。 这反过来导致更好的控制和更可靠的产品。 还指出，现在可能通孔层的完全均匀图案，化学/机械抛光工艺变得更加模式敏感。

公开(公告)号：US5631197A

公开(公告)日：1997-05-20

申请号：US520595

申请日：1995-08-30

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Lung Chen ,  Yuan-Chang Huang

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Lung Chen ,  Yuan-Chang Huang

IPC分类号： H01L21/3105 ,  H01L21/465

CPC分类号： H01L21/31053

摘要： A method for forming a sacrificial planarization layer over an SOG layer which provide a more planar final surface. A substrate is provided with a first insulating layer formed on its surface. A spin-on-glass (SOG) layer is formed over the first insulating layer. The SOG layer has a greater thickness towards the outer edge compared to the central area of the substrate. Next a sacrificial layer is formed over the SOG layer. The sacrificial layer, preferably formed of silicon oxide material, is formed so that the layer has a greater thickness towards the outside of the wafer than in the central area. Next, the sacrificial layer is etched away and portions of the SOG layer are etched. The etch rates of the sacrificial layer, the SOG layer and the first insulating layer are approximately equal so that the planar top SOG surface is transferred to the final top surface after the etch. The resulting surface is planar because the additional sacrificial layer thickness in the outside periphery compensated for the thinner SOG in on the periphery and the faster etch rate on the periphery.

摘要翻译： 一种用于在SOG层上形成牺牲平坦化层的方法，其提供更平面的最终表面。 衬底上设有形成在其表面上的第一绝缘层。 在第一绝缘层上形成旋涂玻璃（SOG）层。 与衬底的中心区域相比，SOG层具有比外边缘更大的厚度。 接下来，在SOG层上形成牺牲层。 优选由氧化硅材料形成的牺牲层被形成为使得该层具有比在中心区域更大于晶片外部的厚度。 接下来，蚀刻掉牺牲层并蚀刻SOG层的部分。 牺牲层，SOG层和第一绝缘层的蚀刻速率大致相等，使得在蚀刻之后，平面顶部SOG表面被转移到最终的顶表面。 所得到的表面是平面的，因为在外围的额外牺牲层厚度补偿了周边较薄的SOG，并且外围蚀刻速率更快。

公开(公告)号：US5599740A

公开(公告)日：1997-02-04

申请号：US558491

申请日：1995-11-16

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/76837

摘要： A method for forming a gap-filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit layer. Formed upon a semiconductor substrate is a patterned integrated circuit layer which is structured with a titanium nitride upper-most layer. The patterned integrated circuit layer also has at least one lower-lying layer formed of a material having a growth rate with respect to ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers greater than the growth rate of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers upon titanium nitride. Formed within and upon the patterned integrated circuit layer is a silicon oxide insulator spacer layer deposited through an ozone assisted Chemical Vapor Deposition (CVD) process. The silicon oxide insulator spacer layer is formed until the surface of the titanium nitride upper-most layer is passivated with the silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is then etched from the surface of the titanium nitride upper-most layer. Finally, additional portions of the silicon oxide insulator spacer layer are sequentially deposited and etched until the surface of the silicon oxide insulator spacer layer over the lower layer(s) of the patterned integrated circuit layer is planar with the upper surface of the titanium nitride upper-most layer of the patterned integrated circuit layer.

摘要翻译： 在图案化集成电路层内形成间隙填充和自平坦化氧化硅绝缘体间隔层的方法。 形成在半导体衬底上的是由氮化钛最上层构成的图案化集成电路层。 图案化集成电路层还具有至少一个下层，其由具有大于臭氧辅助化学气相沉积（CVD）的生长速率的臭氧辅助化学气相沉积（CVD）氧化硅层的生长速率的材料形成。 氮化钛上的氧化硅层。 形成在图案化集成电路层内部和之上的是通过臭氧辅助化学气相沉积（CVD）工艺沉积的氧化硅绝缘体隔离层。 形成氧化硅绝缘体间隔层，直到氮化钛最上层的表面被氧化硅绝缘体隔离层钝化。 然后从氮化钛最上层的表面蚀刻氧化硅绝缘体隔离层。 最后，依次沉积和蚀刻氧化硅绝缘体间隔层的附加部分，直到图案化集成电路层的下层之上的氧化硅绝缘体隔离层的表面与氮化钛上部的上表面平面 最上层的图案化集成电路层。

公开(公告)号：US06657284B1

公开(公告)日：2003-12-02

申请号：US09727634

申请日：2000-12-01

申请人： Lain-Jong Li ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Lain-Jong Li ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L2358

CPC分类号： H01L21/76822 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

摘要翻译： 在形成电介质层的方法中，首先提供衬底。 然后在衬底上形成介电层，其中介电层由包含硅，碳和氮的电介质材料形成。 优选地，氮含量在介电层的厚度内分级，以提供电介质层的上位氮富连续表面层和电介质层的较低位置的氮不良连续层。 该方法考虑了在其中形成有根据该方法形成的电介质层的微电子制造。 该方法提供了所得到的介电层具有较低介电常数和增强的作为基底层的粘合性能。