公开(公告)号：US20210273071A1

公开(公告)日：2021-09-02

申请号：US17322595

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

公开(公告)号：US20210265366A1

公开(公告)日：2021-08-26

申请号：US16798719

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: H01L27/1159 ,  H01L27/12 ,  G11C11/22

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.

公开(公告)号：US20210242208A1

公开(公告)日：2021-08-05

申请号：US17086628

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin

IPC: H01L27/108

Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

公开(公告)号：US20210233931A1

公开(公告)日：2021-07-29

申请号：US17228072

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11578

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US20210183872A1

公开(公告)日：2021-06-17

申请号：US16885362

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18

Abstract: In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.

公开(公告)号：US11037952B2

公开(公告)日：2021-06-15

申请号：US16457223

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/11573 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/28 ,  H01L29/51 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

公开(公告)号：US10978473B2

公开(公告)日：2021-04-13

申请号：US16509728

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11578 ,  H01L21/28

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US20200328148A1

公开(公告)日：2020-10-15

申请号：US16913697

申请日：2020-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/118 ,  H01L27/02

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US20200303456A1

公开(公告)日：2020-09-24

申请号：US16896369

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

公开(公告)号：US10734580B2

公开(公告)日：2020-08-04

申请号：US16397871

申请日：2019-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.