公开(公告)号：US20130180847A1

公开(公告)日：2013-07-18

申请号：US13244466

申请日：2011-09-24

申请人： Takao Yonehara ,  Subramanian Tamilmani ,  Karl-Josef Kramer ,  Jay Ashjaee ,  Mehrdad M. Moslehi ,  Yasuyoshi Miyaji ,  Noriyuki Hayashi ,  Takamitsu Inahara

发明人： Takao Yonehara ,  Subramanian Tamilmani ,  Karl-Josef Kramer ,  Jay Ashjaee ,  Mehrdad M. Moslehi ,  Yasuyoshi Miyaji ,  Noriyuki Hayashi ,  Takamitsu Inahara

IPC分类号： H01L21/02

CPC分类号： C25D11/005 ,  C25D11/32 ,  C25F3/12 ,  C25F7/02 ,  H01L21/0203 ,  H01L21/67086 ,  H01L21/67781 ,  H01L21/68721 ,  H01L21/68771 ,  H01L21/68785 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

摘要翻译： 本公开使得可以高产率地制造多孔半导体层（由诸如多孔硅的单层或多层多孔半导体制成，包括单孔隙率或多孔隙率层）。 一些应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率的多孔硅形成及其随后的氧化）。 此外，本公开适用于光伏技术的MEMS领域，包括传感器和执行器，独立的或与集成半导体微电子，半导体微电子芯片和光电子集成。

公开(公告)号：US20120085278A1

公开(公告)日：2012-04-12

申请号：US13157250

申请日：2011-06-09

申请人： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Jay Ashjaee ,  George D. Kamian ,  David Mordo ,  Takao Yonehara

发明人： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Jay Ashjaee ,  George D. Kamian ,  David Mordo ,  Takao Yonehara

IPC分类号： C30B23/06 ,  H01L21/673 ,  C30B23/02 ,  C23C16/455 ,  C23C16/46

CPC分类号： H01L21/67754 ,  C23C16/45585 ,  C23C16/481 ,  C23C16/54 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/6719 ,  H01L21/67757

摘要： High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.

摘要翻译： 提供了高生产率薄膜沉积方法和工具，其中厚度在小于1微米至100微米范围内的薄膜半导体材料层沉积在反应器中的多个晶片上。 将晶片装载在分批基座上，并且批量基座位于反应器中，使得在基座和反应器的内壁之间形成锥形气体流动空间。 然后将反应性气体引导到锥形气体空间中并遍及每个晶片，从而改善每个晶片和从晶片到晶片的沉积均匀性。

公开(公告)号：US20120034759A1

公开(公告)日：2012-02-09

申请号：US13262915

申请日：2010-04-02

申请人： Kiyofumi Sakaguchi ,  Takao Yonehara ,  Nobuo Kawase ,  Kenji Nakagawa

发明人： Kiyofumi Sakaguchi ,  Takao Yonehara ,  Nobuo Kawase ,  Kenji Nakagawa

IPC分类号： H01L21/30

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/12 ,  H01L24/16 ,  H01L24/90 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.

摘要翻译： 一种制造半导体器件的方法包括在第一半导体衬底的表面侧形成多个第一集成电路的步骤; 在形成在设置在第二半导体衬底上的剥离层上的半导体层中形成多个第二集成电路; 键合两个半导体基板，使得电接合部分彼此结合以形成接合结构; 在所述剥离层处将所述第二半导体衬底与所述接合结构分离，以将形成有所述多个第二集成电路的所述半导体层转移到所述第一半导体衬底; 以及切割第一半导体衬底以获得每个包括第一集成电路和第二集成电路的堆叠芯片。

公开(公告)号：US20110311276A1

公开(公告)日：2011-12-22

申请号：US13254024

申请日：2010-03-01

申请人： Takao Yonehara ,  Yasuyoshi Takai

发明人： Takao Yonehara ,  Yasuyoshi Takai

IPC分类号： G03G15/04 ,  H01L27/15 ,  H01L21/30

CPC分类号： B41J2/45 ,  H01L21/6835 ,  H01L24/83 ,  H01L33/0079 ,  H01L2221/68359 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

摘要： Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.

摘要翻译： 提供了一种用于将布置并连接到第一分离层的功能区域中的至少一个转移到第二基板上的方法，第一分离层设置在第一基板上并且通过处理可分离，其中第二基板上的区域 要转移功能区域具有可通过处理分离的第二分离层。 该方法包括通过接合将第一基板接合到第二基板的步骤，使得功能区域接触第二分离层; 在第一分离层处分离功能区域与第一基板的步骤; 以及在分离步骤之前或之后的步骤，从第二基板的表面形成穿过第二基板和第二分离层的分离槽，该表面与其上具有第二分离层的表面相对。

公开(公告)号：US08053335B2

公开(公告)日：2011-11-08

申请号：US12611791

申请日：2009-11-03

申请人： Takao Yonehara

发明人： Takao Yonehara

IPC分类号： H01L21/52 ,  H01L21/50

CPC分类号： H01L21/0254 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/0079

摘要： A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.

摘要翻译： 一种方法包括在第一衬底上形成含有氧化硅的第一层，部分去除第一层以在第一衬底上形成曝光部分，在第一衬底上用曝光部分沉积非晶氮化镓系化合物半导体，将半导体蒸发 所述第一层在所述第一基板的曝光部分上形成所述半导体的芯，在所述第一基板上形成所述半导体的外延层，以及在所述第一基板上的所述曝光部分上去除所述半导体的外延层，以形成分离 槽。

公开(公告)号：US20110013926A1

公开(公告)日：2011-01-20

申请号：US12922447

申请日：2009-04-28

申请人： Takao Yonehara

发明人： Takao Yonehara

IPC分类号： G03G21/20 ,  F21V5/04 ,  F21V29/00

CPC分类号： B41J2/451

摘要： A light-emitting unit having an arrayed light source comprises a substrate; an arrayed light source group containing the arrayed light source arranged in a first direction; a lens array for focusing the light emitted from light emitting elements constituting the arrayed light source; and a lens support having a cavity formed between arrayed light source group and the lens array; the lens support having a first hole for introducing a fluid into the cavity, and a second hole for discharging the introduced fluid in a second direction crossing the first direction.

摘要翻译： 具有排列光源的发光单元包括基板; 包含沿第一方向排列的排列光源的排列光源组; 用于聚焦从构成阵列光源的发光元件发出的光的透镜阵列; 以及透镜支架，其具有形成在排列的光源组和透镜阵列之间的空腔; 所述透镜支架具有用于将流体引入所述空腔的第一孔，以及用于沿与所述第一方向交叉的第二方向排出所述引入流体的第二孔。

公开(公告)号：US20100110157A1

公开(公告)日：2010-05-06

申请号：US12611739

申请日：2009-11-03

申请人： Takao Yonehara ,  Yasuyoshi Takai

发明人： Takao Yonehara ,  Yasuyoshi Takai

IPC分类号： B41J2/385 ,  H01L21/30 ,  H01L33/00

CPC分类号： H01L33/0079 ,  B41J2/45 ,  H01L21/6835 ,  H01L25/167 ,  H01L27/153 ,  H01L2221/68322 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes arranging a first bonding layer on a first functional region on a first substrate, or a region on a second substrate, bonding the first functional region to the second substrate through the first bonding layer, subjecting a first release layer to a first process to separate the first substrate from the first functional region at the first release layer, arranging a second bonding layer on a second functional region on the first substrate, or a region on a third substrate, bonding the second functional region to the second or third substrate through the second bonding layer, and subjecting a second release layer to a second process to separate the first substrate from the second functional region at the second release layer.

摘要翻译： 一种方法包括：在第一基板上的第一功能区域或第二基板上的区域上布置第一接合层，通过第一接合层将第一功能区域与第二基板接合，使第一释放层进行第一处理 在第一释放层处将第一基板与第一功能区域分开，在第一基板上的第二功能区域或第三基板上的区域上布置第二接合层，将第二功能区域结合到第二或第三基板 通过第二接合层，并且使第二剥离层进行第二工序，以将第一衬底与第二剥离层处的第二功能区分离。

公开(公告)号：US20100109024A1

公开(公告)日：2010-05-06

申请号：US12611770

申请日：2009-11-03

申请人： Takao Yonehara ,  Yasuyoshi Takai

发明人： Takao Yonehara ,  Yasuyoshi Takai

IPC分类号： H01L31/12 ,  H01L21/762 ,  H01L27/15

CPC分类号： H01L27/153 ,  B41J2/45 ,  H01L33/0079

摘要： A method includes arranging a bonding layer of a predetermined thickness on at least one of a first functional region bonded on a release layer, which is capable of falling into a releasable condition when subjected to a process, on a first substrate, and a region, to which the first functional region is to be transferred, on a second substrate; bonding the first functional region to the second substrate through the bonding layer; and separating the first substrate from the first functional region at the release layer.

摘要翻译： 一种方法包括在第一基板和区域上将预定厚度的接合层布置在接合在分离层上的第一功能区域中，该第一功能区域能够在经受处理时落入可释放状态中， 第一功能区域将被转移到第二基板上; 通过所述接合层将所述第一功能区域接合到所述第二基板; 以及在所述剥离层处将所述第一衬底与所述第一功能区分离。

公开(公告)号：US20090061604A1

公开(公告)日：2009-03-05

申请号：US12198838

申请日：2008-08-26

申请人： Ammar Munir Nayfeh ,  Chi On Chui ,  Krishna C. Saraswat ,  Takao Yonehara

发明人： Ammar Munir Nayfeh ,  Chi On Chui ,  Krishna C. Saraswat ,  Takao Yonehara

IPC分类号： H01L21/205

CPC分类号： H01L29/518 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/94

摘要： Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

摘要翻译： 锗电路型结构方便。 在一个示例实施例中，实施多步生长和退火工艺以在包括硅（Si）或含硅材料的衬底上生长含锗（Ge）的材料，例如异质外延锗。 在某些应用中，缺陷通常被限制在硅/锗界面附近，通常阻止含锗材料的上表面的缺陷穿线。 这些方法适用于包括锗MOS电容器，pMOSFET和光电器件在内的各种器件。

公开(公告)号：US07495313B2

公开(公告)日：2009-02-24

申请号：US11188140

申请日：2005-07-22

申请人： Ammar Munir Nayfeh ,  Chi On Chui ,  Krishna C. Saraswat ,  Takao Yonehara

发明人： Ammar Munir Nayfeh ,  Chi On Chui ,  Krishna C. Saraswat ,  Takao Yonehara

IPC分类号： H01L27/082

CPC分类号： H01L29/518 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/94

摘要： Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

摘要翻译： 锗电路型结构方便。 在一个示例实施例中，实施多步生长和退火工艺以在包括硅（Si）或含硅材料的衬底上生长含锗（Ge）的材料，例如异质外延锗。 在某些应用中，缺陷通常被限制在硅/锗界面附近，通常阻止含锗材料的上表面的缺陷穿线。 这些方法适用于包括锗MOS电容器，pMOSFET和光电器件在内的各种器件。