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61.发明授权Nonvolatile semiconductor memory device having element isolating region of trench type 有权具有沟槽型元件隔离区域的非易失性半导体存储器件公开(公告)号：US07939406B2
公开(公告)日：2011-05-10
申请号：US12435842
申请日：2009-05-05
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。
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公开(公告)号：US20110065272A1
公开(公告)日：2011-03-17
申请号：US12948412
申请日：2010-11-17
IPC分类号： H01L21/768 , B32B38/04
CPC分类号： H01L23/5283 , H01L21/0217 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L45/06 , H01L2924/0002 , Y10T156/1057 , H01L2924/00
摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。
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公开(公告)号：US20110024825A1
公开(公告)日：2011-02-03
申请号：US12898914
申请日：2010-10-06
IPC分类号： H01L29/792
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.
摘要翻译： 根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。 有源区域和元件隔离区域沿第一方向交替布置。 从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。
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公开(公告)号：US07825439B2
公开(公告)日：2010-11-02
申请号：US12191592
申请日：2008-08-14
IPC分类号： H01L29/768
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.
摘要翻译： 根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。 有源区域和元件隔离区域沿第一方向交替布置。 从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。
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公开(公告)号：US20090230450A1
公开(公告)日：2009-09-17
申请号：US12394929
申请日：2009-02-27
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译： 非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。 在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。 外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。
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66.发明授权Nonvolatile semiconductor memory device having element isolating region of trench type 有权具有沟槽型元件隔离区域的非易失性半导体存储器件公开(公告)号：US07573092B2
公开(公告)日：2009-08-11
申请号：US11556026
申请日：2006-11-02
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。
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公开(公告)号：US07538380B2
公开(公告)日：2009-05-26
申请号：US11556299
申请日：2006-11-03
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
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公开(公告)号：US20090020744A1
公开(公告)日：2009-01-22
申请号：US12163145
申请日：2008-06-27
IPC分类号： H01L45/00 , H01L23/52 , H01L21/4763
CPC分类号： H01L23/5283 , H01L21/0217 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L45/06 , H01L2924/0002 , Y10T156/1057 , H01L2924/00
摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。
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公开(公告)号：US20080181009A1
公开(公告)日：2008-07-31
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译： 半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据 在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行 在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入 细胞再次。
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70.发明申请NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权具有元件分离区域的非挥发性半导体存储器件公开(公告)号：US20070057310A1
公开(公告)日：2007-03-15
申请号：US11556026
申请日：2006-11-02
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。
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