公开(公告)号：US08664108B2

公开(公告)日：2014-03-04

申请号：US12948412

申请日：2010-11-17

申请人： Makoto Mizukami ,  Takeshi Kamigaichi

发明人： Makoto Mizukami ,  Takeshi Kamigaichi

IPC分类号： H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

公开(公告)号：US07855457B2

公开(公告)日：2010-12-21

申请号：US12163145

申请日：2008-06-27

申请人： Makoto Mizukami ,  Takeshi Kamigaichi

发明人： Makoto Mizukami ,  Takeshi Kamigaichi

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。

公开(公告)号：US20110065272A1

公开(公告)日：2011-03-17

申请号：US12948412

申请日：2010-11-17

申请人： Makoto MIZUKAMI ,  Takeshi Kamigaichi

发明人： Makoto MIZUKAMI ,  Takeshi Kamigaichi

IPC分类号： H01L21/768 ,  B32B38/04

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。

公开(公告)号：US20090020744A1

公开(公告)日：2009-01-22

申请号：US12163145

申请日：2008-06-27

申请人： Makoto Mizukami ,  Takeshi Kamigaichi

发明人： Makoto Mizukami ,  Takeshi Kamigaichi

IPC分类号： H01L45/00 ,  H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。

公开(公告)号：US08314455B2

公开(公告)日：2012-11-20

申请号：US13156727

申请日：2011-06-09

申请人： Yasuhiro Shiino ,  Atsuhiro Sato ,  Takeshi Kamigaichi ,  Fumitaka Arai

发明人： Yasuhiro Shiino ,  Atsuhiro Sato ,  Takeshi Kamigaichi ,  Fumitaka Arai

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.

摘要翻译： 非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。 在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。 外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

公开(公告)号：US08279679B2

公开(公告)日：2012-10-02

申请号：US12979796

申请日：2010-12-28

申请人： Takeshi Kamigaichi ,  Kenji Sawamura

发明人： Takeshi Kamigaichi ,  Kenji Sawamura

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A control circuit is configured to perform, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution that is the maximum distribution of the threshold voltage distributions. The circuit is configured to apply, at least during a verify operation in a first write operation conducted before a second write operation that completes writing to the first threshold voltage distribution, a second read-pass voltage lower than the first read-pass voltage to the unselected memory cell, and apply to the semiconductor layer and the source-line a positive voltage.

摘要翻译： 控制电路被配置为在对存储器单元的写入操作和用于验证存储器单元的阈值电压的验证操作中执行电压控制，以向存储器单元提供阈值电压分布。 该电路被配置为在从存储器单元的读取操作中将阈值电压分布的下限和上限之间的读取电压应用于所选择的存储器单元，并将其应用于未选择的存储器单元的第一读取通过电压 超过作为阈值电压分布的最大分布的第一阈值电压分布的上限。 该电路被配置为至少在第二写入操作期间在完成对第一阈值电压分布的写入的第二写入操作期间的验证操作期间施加低于第一读通过电压的第二读通过电压 未选择的存储单元，并且应用于半导体层和源极线的正电压。

公开(公告)号：US08026546B2

公开(公告)日：2011-09-27

申请号：US12434305

申请日：2009-05-01

申请人： Takeshi Murata ,  Takeshi Kamigaichi

发明人： Takeshi Murata ,  Takeshi Kamigaichi

IPC分类号： H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.

摘要翻译： 非易失性半导体存储器件包括具有第一选择晶体管的第一堆叠单元和形成在半导体衬底上的第二选择晶体管和具有第一绝缘层的第二堆叠单元和在第一堆叠单元的上表面上交替堆叠的第一导电层。 第二堆叠单元包括与第一绝缘层和第一导电层的侧壁接触形成的第二绝缘层，与用于存储电荷的第二绝缘层接触形成的电荷存储层，形成为接触的第三绝缘层 与电荷存储层形成的第一半导体层以及与第三绝缘层接触形成的层叠方向延伸的第一半导体层，一端与第一选择晶体管的一个扩散层连接，另一端与扩散层连接 的第二选择晶体管。

公开(公告)号：US20110186921A1

公开(公告)日：2011-08-04

申请号：US13085884

申请日：2011-04-13

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

公开(公告)号：US07939908B2

公开(公告)日：2011-05-10

申请号：US11510584

申请日：2006-08-28

申请人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Takeshi Kamigaichi

发明人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Takeshi Kamigaichi

IPC分类号： H01L21/76

CPC分类号： H01L27/11526 ,  G11C16/0408 ,  G11C16/08 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404

摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

公开(公告)号：US20100065900A1

公开(公告)日：2010-03-18

申请号：US12560783

申请日：2009-09-16

申请人： Takeshi MURATA ,  Takeshi Kamigaichi ,  Itaru Kawabata ,  Shinya Takahashi

发明人： Takeshi MURATA ,  Takeshi Kamigaichi ,  Itaru Kawabata ,  Shinya Takahashi

IPC分类号： H01L29/8605 ,  H01L29/792 ,  H01L23/48

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a resistance element. The resistance element includes a first and second conductive films, second insulating film, and contact plugs. The first conductive film is formed on a semiconductor substrate with a first insulating film interposed therebetween. The second insulating film is formed on the first conductive film. The second conductive film is formed on the second insulating film. In the first connection portion, the second insulating film is removed. The first connection portion connects the first conductive film and the second conductive film together. The contact plugs are formed on the second conductive film. The contact plugs are arranged such that a region located on the second conductive film and immediately above the connection portion is sandwiched between the contact plugs.

摘要翻译： 半导体器件包括电阻元件。 电阻元件包括第一和第二导电膜，第二绝缘膜和接触插塞。 第一导电膜形成在半导体衬底上，其间插入有第一绝缘膜。 第二绝缘膜形成在第一导电膜上。 第二导电膜形成在第二绝缘膜上。 在第一连接部分中，去除第二绝缘膜。 第一连接部分将第一导电膜和第二导电膜连接在一起。 接触插塞形成在第二导电膜上。 接触插塞被布置成使得位于第二导电膜上并紧邻连接部分的区域夹在接触插塞之间。