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    Dynamic Address Translation With Translation Exception Qualifier
    62.
    发明申请
    Dynamic Address Translation With Translation Exception Qualifier 有权
    动态地址转换与翻译异常限定符

    公开(公告)号：US20120084488A1

    公开(公告)日：2012-04-05

    申请号：US13312079

    申请日：2011-12-06

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS
    63.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS 失效
    方法，系统和计算机程序产品，用于提供GUEST2 QUIESCE要求的过滤

    公开(公告)号：US20090217264A1

    公开(公告)日：2009-08-27

    申请号：US12037887

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    发明人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45558 ,  G06F2009/45566

    摘要： A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.

    摘要翻译： 一种用于提供二级客户（G2）静默请求过滤的方法，系统和计算机程序产品。 该方法包括在当前或先前执行在逻辑分区中的二级虚拟机管理程序下运行的G2的处理器处接收G2停顿中断请求。 G2包括当前区域和G2虚拟机（VM）标识符。 静默中断请求指定启动区域和启动G2 VM标识符。 确定G2停顿中断请求是否可以被处理器过滤。 该确定响应于当前的G2 VM标识符，当前区域，起始区域和起始G2 VM标识符。 响应于确定可以过滤G2静默中断请求，在处理器处对G2静默中断请求进行过滤。 因此，提供了在逻辑分区中运行的G2虚拟机之间的过滤。

    DIAGNOSE INSTRUCTION FOR SERIALIZING PROCESSING
    65.
    发明申请
    DIAGNOSE INSTRUCTION FOR SERIALIZING PROCESSING 有权
    用于串行处理的诊断指令

    公开(公告)号：US20120216195A1

    公开(公告)日：2012-08-23

    申请号：US13459167

    申请日：2012-04-28

    申请人： Lisa C. Heller

    发明人： Lisa C. Heller

    IPC分类号： G06F9/455 ,  G06F9/312

    CPC分类号： G06F9/30087 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30185 ,  G06F9/45533 ,  G06F9/52

    摘要： A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

    摘要翻译： 提供系统序列化功能以便于允许多个处理器更新相同资源的那些环境中的处理。 系统序列化功能用于在多处理环境中促进处理，其中客人和主机使用锁来提供序列化。 系统序列化功能包括在主机获取锁定之后发出的诊断指令，消除了客人获取锁定的需要。

    System, method and computer program product for providing a new quiesce state
    66.
    发明授权
    System, method and computer program product for providing a new quiesce state 有权
    用于提供新的静止状态的系统，方法和计算机程序产品

    公开(公告)号：US08032716B2

    公开(公告)日：2011-10-04

    申请号：US12037904

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

    发明人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F12/1072 ,  G06F12/1475

    摘要： A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

    摘要翻译： 一种用于提供新的静默状态的系统，方法和计算机程序产品。 该方法包括从系统控制器从启动处理器接收静默请求。 停顿请求被发送到多个处理器。 在系统控制器处接收到通知，处理器已经完成清除其翻译的旁边的缓冲区（TLB）。 一旦系统资源的更新完成，系统控制器就会从启动处理器接收快速静默复位命令。 向处理器指示响应于接收到快速静默复位命令可以丢弃块转换限制，从而允许处理器继续处理而没有块转换限制。

    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE
    68.
    发明申请
    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE 有权
    用于提供新的QUIESCE状态的系统，方法和计算机程序产品

    公开(公告)号：US20090216928A1

    公开(公告)日：2009-08-27

    申请号：US12037904

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

    发明人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

    IPC分类号： G06F13/24

    CPC分类号： G06F12/1027 ,  G06F12/1072 ,  G06F12/1475

    摘要： A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

    摘要翻译： 一种用于提供新的静默状态的系统，方法和计算机程序产品。 该方法包括从系统控制器从启动处理器接收静默请求。 停顿请求被发送到多个处理器。 在系统控制器处接收到通知，处理器已经完成清除其翻译的旁边的缓冲区（TLB）。 一旦系统资源的更新完成，系统控制器就会从启动处理器接收快速静默复位命令。 向处理器指示响应于接收到快速静默复位命令可以丢弃块转换限制，从而允许处理器继续处理而没有块转换限制。

    Method and apparatus for enabling an interpretive execution subset
    69.
    发明授权
    Method and apparatus for enabling an interpretive execution subset 失效
    用于启用解释执行子集的方法和装置

    公开(公告)号：US5317754A

    公开(公告)日：1994-05-31

    申请号：US602029

    申请日：1990-10-23

    申请人： Geoffrey O. Blandy ,  Lisa C. Heller ,  Robert E. Murray

    发明人： Geoffrey O. Blandy ,  Lisa C. Heller ,  Robert E. Murray

    IPC分类号： G06F9/48 ,  G06F12/10 ,  G06F9/46

    CPC分类号： G06F9/4843 ,  G06F12/1036

    摘要： An apparatus and method are established for recognizing guest virtual machines which require only a subset of interpretive execution facilities. The interpretive execution initialization process recognizes subset candidates and bypasses initialization of those facilities not required by the candidates. The candidates are typically short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement. The translation lookaside buffer operation is modified to flag subset guest entries as host entries and to associate a unique segment table origin with each subset guest. This allows the TLB entries to remain between guest machine dispatches eliminating TLB purge time and allowing potential reuse of TLB entries if the same guest is repeatedly dispatched within a short time period. The guest machine state description is modified to flag subset candidates based on address translation and timing requirements. Initialization of timing facilities is bypassed in certain subset modes further reducing initialization overhead.

    摘要翻译： 建立了一种用于识别仅需要解释性执行设施的子集的客体虚拟机的装置和方法。 解释执行初始化过程识别子集候选者，并绕过候选人不需要的这些设施的初始化。 候选人通常是短期工作，并且初始化和终止开销的减少创造了显着的性能改进。 修改翻译后备缓冲区操作被修改为将子组客户条目标记为主机条目，并将唯一段表原点与每个子组客户关联。 这允许TLB条目保留在客机调度之间，消除TLB清除时间，并允许在短时间内重复发送同一客户端的TLB条目的潜在重用。 根据地址转换和时序要求修改访客机状态描述以标记子集候选。 定时设备的初始化在某些子集模式中被绕过，从而进一步降低了初始化开销。

    Method and apparatus to limit millicode routine end branch prediction
    70.
    发明授权
    Method and apparatus to limit millicode routine end branch prediction 有权
    终止分支预测的方法和装置

    公开(公告)号：US09086886B2

    公开(公告)日：2015-07-21

    申请号：US12821690

    申请日：2010-06-23

    申请人： Brian R. Prasky ,  James J. Bonanno ,  Lisa C. Heller

    发明人： Brian R. Prasky ,  James J. Bonanno ,  Lisa C. Heller

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3017

    摘要： A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.

    摘要翻译： 一个计算系统方法，程序和硬件相关的millicode预测与特定的millicode例程接收架构式的代码，并将millicode存储在内部存储器中。 计算机系统处理器的流水线用于预测和选择分支目标缓冲器（BTB）目标地址。 一种计算机微码控制，其使得能够使用毫秒代码程序的多个用户程序之间的操作系统（O / S）多任务控制，并且通过使用分支目标缓冲器（BTB）预测来确保程序不相互干扰 分支目标，以确保毫秒代码程序在执行所述毫代码路由所要求的操作之前不会从所述毫代码程序外部获取，所述分支目标缓冲器预测采用用于预测毫米编码的分支毫代数条目和毫分节结束指令的相关机制，并且用于关联millicode 用特定的millicode例程结束预测。