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    IMINO DERIVATIVES, PROCESS FOR PREPARATION THEREOF, AND INSECTICIDES CONTAINING SAME
    63.
    发明申请
    IMINO DERIVATIVES, PROCESS FOR PREPARATION THEREOF, AND INSECTICIDES CONTAINING SAME 审中-公开
    IMINO衍生物，其制备方法和含有其的杀虫剂

    公开(公告)号：US20120277440A1

    公开(公告)日：2012-11-01

    申请号：US13520668

    申请日：2011-01-06

    申请人： Shinzo Kagabu ,  Satoru Kumazawa ,  Tsumoru Watanabe ,  Taiji Miyake ,  Masahiro Nomura ,  Satoshi Nakamura ,  Masaaki Mitomi

    发明人： Shinzo Kagabu ,  Satoru Kumazawa ,  Tsumoru Watanabe ,  Taiji Miyake ,  Masahiro Nomura ,  Satoshi Nakamura ,  Masaaki Mitomi

    IPC分类号： C07D417/06

    CPC分类号： C07D417/06 ,  A01N43/78 ,  C07D417/14

    摘要： To provide a novel imino derivative capable of being an insecticide compound which is excellent in characteristics such as sustained effects and a broad spectrum.An imino derivative represented by Formula (A) shown below: wherein “Ar” represents a heterocyclic group which may have a substituent on the ring, “X” represents a sulfur atom or CH2, NR; “R” represents a hydrogen atom or an alkyl group; “Ya” is selected from “C(═S)NR1R2”, “C(═S)SR3”, “C(═O)SR4”, “C(═S)OR4”, “SO2Zα”, and “OZβ”; and, each of “R1” to “R4”, “Zα”, and “Zβ” represents a hydrogen atom or a certain substituent; is provided.

    摘要翻译： 提供能够成为持续效果和广谱特性优异的杀虫剂化合物的新型亚氨基衍生物。 由下式（A）表示的亚氨基衍生物：其中Ar表示可在环上具有取代基的杂环基，X表示硫原子或CH2，NR; R表示氢原子或烷基; Ya选自C（= S）NR1R2，C（= S）SR3，C（= O）SR4，C（= ORS）OR4，SO2Zα和OZ。 并且R 1至R 4，Z a和Z bb中的每一个; 表示氢原子或某一取代基; 被提供。

    Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path
    64.
    发明授权
    Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path 失效
    具有多个延迟路径的半导体集成电路装置和能够阻止延迟路径中的信号传输的控制器

    公开(公告)号：US08237473B2

    公开(公告)日：2012-08-07

    申请号：US12588993

    申请日：2009-11-04

    申请人： Masahiro Nomura

    发明人： Masahiro Nomura

    IPC分类号： H03L7/00

    CPC分类号： H03K5/135 ,  H03K5/26

    摘要： A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

    摘要翻译： 多个延迟路径并联连接在与时钟信号CLK同步操作的两个同步操作电路之间，并且使能信号的传输。 延迟检测单元检测多个延迟路径的各个延迟时间，并且控制单元基于来自延迟检测单元的检测结果从多个延迟路径中选择一个延迟路径，并且控制信号传输阻塞 除了所选择的一个延迟路径之外的延迟路径。

    Semiconductor integrated circuit device
    65.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US08008659B2

    公开(公告)日：2011-08-30

    申请号：US11261753

    申请日：2005-10-31

    申请人： Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

    发明人： Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

    IPC分类号： H01L23/58 ,  H01L29/10 ,  H03K3/01

    CPC分类号： H03K19/0013 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep. A control signal is transmitted to the substrate bias generating circuit such that the substrate bias is made deep when the substrate leakage current is smaller than the subthreshold leakage current and such that the substrate bias is made shallow when the substrate leakage current is larger than the subthreshold leakage current.

    摘要翻译： 控制衬底偏置使得漏电流最小。 一种半导体集成电路装置，包括利用泄漏检测用MOSFET检测泄漏电流的漏电检测电路，根据来自漏电检测电路的输出产生控制信号的控制电路，将衬底偏置变化的衬底偏置产生电路 控制信号的控制电路以及具有与各漏电检测用MOSFET相同特性的MOSFET的受控电路。 泄漏检测电路检测衬底偏置变深时包括的衬底漏电流，以及随着衬底偏压变深而减小的亚阈值漏电流。 控制信号被传送到衬底偏置产生电路，使得当衬底漏电流小于亚阈值漏电流时衬底偏压变深，并且当衬底泄漏电流大于次阈值时衬底偏置变浅 漏电流。

    Power supply voltage control circuit
    67.
    发明申请
    Power supply voltage control circuit 审中-公开
    电源电压控制电路

    公开(公告)号：US20100295530A1

    公开(公告)日：2010-11-25

    申请号：US12662710

    申请日：2010-04-29

    申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

    发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

    IPC分类号： H02J4/00

    CPC分类号： H02M3/157

    摘要： A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal.

    摘要翻译： 电源电压控制电路控制提供给执行特定信号处理的目标电路的电源电压。 电源电压控制电路包括控制信号产生电路，当提供给目标电路的电源电压从第一电源电压增加到第二电源电压时，选择性地产生第一和第二控制信号，第二电源电压 高于第一电源电压的电源电压，以及基于第一控制信号将电源电压提高到第二电源电压的电压电平的电源电路，或者将电源电压提高到高于 并且随后基于第二控制信号将电源电压降低到第二电源电压。

    Semiconductor Integrated Circuit Device
    69.
    发明申请
    Semiconductor Integrated Circuit Device 有权
    半导体集成电路器件

    公开(公告)号：US20080191791A1

    公开(公告)日：2008-08-14

    申请号：US11813502

    申请日：2006-01-06

    申请人： Masahiro Nomura ,  Koichi Takeda

    发明人： Masahiro Nomura ,  Koichi Takeda

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0008

    摘要： A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

    摘要翻译： 一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。 在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为 保证运行速度。

    Semiconductor Device and Method for Production Thereof
    70.
    发明申请
    Semiconductor Device and Method for Production Thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US20080029821A1

    公开(公告)日：2008-02-07

    申请号：US11632352

    申请日：2005-07-04

    申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

    发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

    摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

    摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。