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公开(公告)号：US20160240540A1
公开(公告)日：2016-08-18
申请号：US14620212
申请日：2015-02-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Chih-Sen Huang , Yi-Wei Chen
IPC: H01L27/11 , H01L29/06 , H01L23/535 , H01L29/78
CPC classification number: H01L27/1104 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L27/3223 , H01L29/0649 , H01L29/66545
Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.
Abstract translation: 提供一种半导体结构，包括基板，多个第一半导体器件，多个第二半导体器件和多个虚拟插槽触点。 衬底具有器件区域，其中器件区域包括第一功能区域和第二功能区域，并且虚设区域设置在其间。 第一半导体器件和多个第一时隙触点设置在第一功能区域中。 第二半导体器件和多个第二槽触点设置在第二功能区域中。 虚拟插槽触点设置在虚拟区域中。
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公开(公告)号：US20160104646A1
公开(公告)日：2016-04-14
申请号：US14514374
申请日：2014-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Tsung-Hung Chang , Jia-Rong Wu , Ching-Ling Lin , Yi-Hui Lee , Chih-Sen Huang , Yi-Wei Chen
IPC: H01L21/8234 , H01L21/311 , H01L21/285 , H01L21/768
CPC classification number: H01L21/823475 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L21/823431
Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.
Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。
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公开(公告)号：US09263392B1
公开(公告)日：2016-02-16
申请号：US14529129
申请日：2014-10-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Ling Lin , Chih-Sen Huang , Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Yi-Hui Lee , Yi-Wei Chen
IPC: H01L21/336 , H01L23/535 , H01L29/78 , H01L21/8234 , H01L21/768 , H01L21/02 , H01L21/311
CPC classification number: H01L21/31144 , H01L21/0217 , H01L21/7682 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L23/485 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属栅极的基板和围绕金属栅极的层间电介质（ILD）层; 去除所述金属浇口的一部分以形成凹部; 以及在所述凹部中和所述ILD层上沉积掩模层，同时在所述凹部中形成空隙。
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公开(公告)号：US20250107454A1
公开(公告)日：2025-03-27
申请号：US18976359
申请日：2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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公开(公告)号：US12262647B2
公开(公告)日：2025-03-25
申请号：US18592553
申请日：2024-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
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Patent Agency Ranking
公开(公告)号：US12133474B2
公开(公告)日：2024-10-29
申请号：US18373295
申请日：2023-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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公开(公告)号：US20240268124A1
公开(公告)日：2024-08-08
申请号：US18636306
申请日：2024-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
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公开(公告)号：US12029044B2
公开(公告)日：2024-07-02
申请号：US18127651
申请日：2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
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公开(公告)号：US20230238043A1
公开(公告)日：2023-07-27
申请号：US18127651
申请日：2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H10B61/00 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
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公开(公告)号：US11646069B2
公开(公告)日：2023-05-09
申请号：US17460348
申请日：2021-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: G11C11/161 , H01L27/222 , H01L27/224 , H01L43/02 , H01L43/12
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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