公开(公告)号：US06693821B2

公开(公告)日：2004-02-17

申请号：US09893830

申请日：2001-06-28

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： G11C1100

CPC分类号： H01L27/24 ,  G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77

摘要： Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了低串扰电阻交叉点存储器件，以及制造和使用方法。 存储装置包括使用插入在上电极和下电极的交叉点处的钙钛矿材料形成的钻头。 每个位具有响应于施加一个或多个电压脉冲而可以在一定范围内的值改变的电阻率。 可以使用电压脉冲来增加比特的电阻率，降低比特的电阻率或确定比特的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06649957B2

公开(公告)日：2003-11-18

申请号：US10345725

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

IPC分类号： H01L2976

CPC分类号： H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

摘要翻译： 描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层 绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。 还描述了形成多晶存储器结构的方法。 沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。 绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

公开(公告)号：US06586260B2

公开(公告)日：2003-07-01

申请号：US09820078

申请日：2001-03-28

申请人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

公开(公告)号：US06583003B1

公开(公告)日：2003-06-24

申请号：US10256362

申请日：2002-09-26

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L218242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a 1T1R resistive memory array. The method of forming a 1T1R resistive memory array structure on a semiconductor substrate comprises forming an array of transistors comprising a polycide/oxide/nitride gate stack with nitride sidewalls, the transistors comprising a source and a drain region adjacent to the gate stack. An insulating layer is deposited and planarized level with the polycide/oxide/nitride gate stack. Bit contact openings are etched to expose the drain region. Bottom electrodes are formed by depositing and planarizing a metal. A resistive memory material is deposited over the bottom electrodes. Top electrodes are formed over the resistive memory material. The 1T1R resistive memory array may be connected to support circuits that are formed on the same substrate as the memory array. The support circuits may share many of the process steps with the formation of the transistors for the memory array.

摘要翻译： 提供了一种用于形成1T1R电阻式存储器阵列的方法。 在半导体衬底上形成1T1R电阻性存储器阵列结构的方法包括形成包括具有氮化物侧壁的多晶硅/氧化物/氮化物栅叠层的晶体管阵列，所述晶体管包括与栅叠层相邻的源区和漏区。 绝缘层与多晶硅/氧化物/氮化物栅极叠层沉积并平坦化。 蚀刻位触点开口以露出漏极区域。 通过沉积和平坦化金属形成底部电极。 电阻性记忆材料沉积在底部电极上。 顶部电极形成在电阻式存储器材料上。 1T1R电阻式存储器阵列可以连接到形成在与存储器阵列相同的衬底上的支撑电路。 支持电路可以与存储器阵列的晶体管的形成共享许多处理步骤。

公开(公告)号：US06579793B2

公开(公告)日：2003-06-17

申请号：US09820224

申请日：2001-03-27

申请人： Wei-Wei Zhuang ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23C1618

CPC分类号： C23C16/18 ,  C23C16/56 ,  H01L21/28556

摘要： A fabrication process provides for achieving high adhesion of CVD copper thin films on metal nitride substrates, and in particular, on substrates having an outermost TaN layer. The method comprises introducing a certain amount of water vapor to the initial copper thin film deposition stage and reducing the amount of fluorine in the interface of the copper and metal nitride substrate. These two process steps result in a copper thin film having improved adhesion to metal nitride substrates, including TaN substrates.

摘要翻译： 制造工艺提供了在金属氮化物衬底上，特别是在具有最外层TaN层的衬底上实现CVD铜薄膜的高附着性。 该方法包括将一定量的水蒸汽引入初始铜薄膜沉积阶段并减少铜和金属氮化物衬底的界面中的氟的量。 这两个工艺步骤导致具有改善的与金属氮化物衬底（包括TaN衬底）的粘附性的铜薄膜。

公开(公告)号：US06576293B2

公开(公告)日：2003-06-10

申请号：US09817836

申请日：2001-03-26

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  David R. Evans

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： C23C1618

CPC分类号： H01L21/28556

摘要： A method of forming a copper thin film by chemical vapor deposition, includes introducing a wafer into a chemical vapor deposition chamber; humidifying helium gas with water to form a wet helium gas for use as the atmosphere in the chemical vapor deposition chamber; depositing a copper seed layer at a wet helium flow rate of between about 5.0 sccm and 20.0 sccm during a wafer temperature rise from ambient temperature to between about 150° C. to 230° C.; and depositing a copper thin film layer at a wet helium flow rate of between about 0.2 sccm to 1.0 sccm and at a temperature of between about 150° C. to 230° C.

公开(公告)号：US06534326B1

公开(公告)日：2003-03-18

申请号：US10099186

申请日：2002-03-13

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

摘要翻译： 描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层 绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。 还描述了形成多晶存储器结构的方法。 沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。 绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

公开(公告)号：US06372034B1

公开(公告)日：2002-04-16

申请号：US09687827

申请日：2000-10-12

申请人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/31691

摘要： A method of preparing a PGO solution for spin coating includes preparing a 2-methoxyethanol organic solvent; adding Pb(OCH3CO)2.3H2O to the organic solvent at ambient temperature and pressure in a nitrogen-filled glaved box to form Pb in methoxyethanol; refluxing the solution in a nitrogen atmosphere at 150° C. for at least two hours; fractionally distilling the refluxed solution at approximately 150° C. to remove all of the water from the solution; cooling the solution to room temperature; determining the Pb concentration of the solution; adding the 2-methoxyethanol solution to the Pb 2-methoxyethanol until a desired Pb concentration is achieved; combining Ge(OR)4, where R is taken the group of Rs consisting of CH2CH3 and CH(CH3)2, and 2-methoxyethanol; and adding Ge(OR)4 2-methoxyethanol to PbO 2-methoxyethanol to form the PGO solution having a predetermined metal ion concentration and a predetermined Pb:Ge molar ration.

摘要翻译： 制备用于旋涂的PGO溶液的方法包括制备2-甲氧基乙醇有机溶剂; 在环境温度和压力下，在氮气充填的玻璃箱中加入Pb（OCH 3 CO）2.3H 2 O至有机溶剂中以在甲氧基乙醇中形成Pb; 将溶液在氮气气氛中在150℃下回流至少2小时; 在大约150℃下将回流的溶液分馏，以从溶液中除去所有的水; 将溶液冷却至室温; 测定溶液的Pb浓度; 将2-甲氧基乙醇溶液加入到Pb 2-甲氧基乙醇中直到达到所需的Pb浓度; 组合Ge（OR）4，其中R是由CH 2 CH 3和CH（CH 3）2组成的基团和2-甲氧基乙醇; 并向PbO 2 - 甲氧基乙醇中加入Ge（OR）4 2-甲氧基乙醇以形成具有预定的金属离子浓度和预定的Pb:Ge摩尔比的PGO溶液。

公开(公告)号：US07402456B2

公开(公告)日：2008-07-22

申请号：US10831677

申请日：2004-04-23

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/44

CPC分类号： H01L45/04 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.

摘要翻译： 提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。 该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。 在一个方面，第一晶体结构是无定形或弱结晶。 然后，响应于单极脉冲改变PCMO膜的电阻状态。 另一方面，PCMO薄膜具有多晶结构。 然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

公开(公告)号：US07192792B2

公开(公告)日：2007-03-20

申请号：US11066592

申请日：2005-02-24

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/66 ,  H01L31/111

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use, including a method of changing an electrically programmable resistance cross point memory bit. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法，包括改变电可编程电阻交叉点存储器位的方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 位于上电极和下电极的交叉点处的有源层内的位区域具有响应于一个或多个电压脉冲的施加而可以在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。