公开(公告)号：US20060059273A1

公开(公告)日：2006-03-16

申请号：US10942422

申请日：2004-09-16

申请人： Michael Carnevale ,  Scott Clark ,  David Hill ,  Charles Johns ,  Thomas Pokrandt ,  Jeffrey Ruedinger ,  Dorothy Thelen

发明人： Michael Carnevale ,  Scott Clark ,  David Hill ,  Charles Johns ,  Thomas Pokrandt ,  Jeffrey Ruedinger ,  Dorothy Thelen

IPC分类号： G06F15/16

CPC分类号： H04L1/188

摘要： The present invention provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

摘要翻译： 本发明提供发送信封并回复信封。 发射机被配置为发送信封。 接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。 发送缓冲器耦合到发送器。 接收缓冲器耦合到接收器。 重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。 如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。 这导致从发射机和接收机两者发送的信封总数的减少。

公开(公告)号：US20060031835A1

公开(公告)日：2006-02-09

申请号：US10912479

申请日：2004-08-05

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F9/46

CPC分类号： G06F1/3203

摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

公开(公告)号：US20050216610A1

公开(公告)日：2005-09-29

申请号：US10809553

申请日：2004-03-25

申请人： Charles Johns ,  James Kahle ,  Peichun Liu ,  Thuong Truong

发明人： Charles Johns ,  James Kahle ,  Peichun Liu ,  Thuong Truong

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F12/0835 ,  G06F12/0837 ,  G06F12/0862

摘要： The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

摘要翻译： 本发明提供了一种用于在支持DMA机制和高速缓存的系统中提供高速缓存管理命令的方法和系统。 DMA机制由处理器设置。 处理器上运行的软件会生成缓存管理命令。 DMA机制执行命令，从而实现高速缓存的软件程序管理。 这些命令包括用于将数据写入缓存的命令，从高速缓存加载数据，以及用于在不再需要的情况下将数据标记在缓存中。 缓存可以是系统缓存或DMA高速缓存。

公开(公告)号：US20050160239A1

公开(公告)日：2005-07-21

申请号：US10759939

申请日：2004-01-16

申请人： Charles Johns

发明人： Charles Johns

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0835 ,  G06F12/0831 ,  G06F12/0879

摘要： In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.

摘要翻译： 在多处理器系统中，包括主处理器和从属处理器，高速缓存一致性控制器和地址集中器件; 描述了一种改进相干数据传输的方法。 生成命令事务，以及来自启动器的后续命令。 标签添加到响应或进一步请求响应，流在高速公交车。 每个处理器将突发命令分离为多个缓存线请求时，侦听和累积侦听器会扩展缓存引用请求。 包含缓存线队列功能的地址集中器，向全局序列化设备发送流量事务请求，其中排队过程优先处理标记并在处理器之间协调结果。 缓存为每个受影响的线路发出单个突发命令。 发生系统一致性，性能和延迟改进。 提供对相干处理器之间的突发传输的额外支持。

公开(公告)号：US20050125581A1

公开(公告)日：2005-06-09

申请号：US10730952

申请日：2003-12-09

申请人： Jeffrey Brown ,  Scott Clark ,  Charles Johns ,  Takeshi Yamazaki

发明人： Jeffrey Brown ,  Scott Clark ,  Charles Johns ,  Takeshi Yamazaki

IPC分类号： G06F13/14 ,  G06F13/362

CPC分类号： G06F13/3625

摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

公开(公告)号：US20050111354A1

公开(公告)日：2005-05-26

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/24 ,  H04L12/26

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20050097280A1

公开(公告)日：2005-05-05

申请号：US10697897

申请日：2003-10-30

申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0284 ,  G06F13/1652

摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自身的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

公开(公告)号：US20050097231A1

公开(公告)日：2005-05-05

申请号：US10697903

申请日：2003-10-30

申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F3/00 ,  G06F3/14 ,  G09G5/14

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

公开(公告)号：US07590774B2

公开(公告)日：2009-09-15

申请号：US11291735

申请日：2005-12-01

申请人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

发明人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

IPC分类号： G06F13/28 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F13/28

摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

摘要翻译： 公开了用于有效地切换处理元件之间的上下文的系统和方法。 这些系统和方法可以将处理元件的上下文传送到存储位置。 使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。 然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

公开(公告)号：US20080005374A1

公开(公告)日：2008-01-03

申请号：US11844336

申请日：2007-08-23

申请人： Scott Clark ,  Charles Johns ,  James Kahle

发明人： Scott Clark ,  Charles Johns ,  James Kahle

IPC分类号： G06F3/00

CPC分类号： G06F13/385

摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.

摘要翻译： 介绍了灵活多协议的系统和方法。 可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。 在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。 在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。