公开(公告)号：US20080123390A1

公开(公告)日：2008-05-29

申请号：US11882694

申请日：2007-08-03

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： G11C11/00 ,  H01L21/16

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/24

摘要： A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 在非易失性存储器件中，第一导电类型的至少一个第一半导体层可以在衬底的一部分上彼此间隔开形成。 多个第一电阻变化存储层可以接触至少一个第一半导体层中的每一个的第一侧壁。 与第一导电类型相反的第二导电类型的多个第二半导体层可以插入在至少一个第一半导体层和多个第一电阻变化存储层中的每一个的第一侧壁之间。 多个位线电极可以连接到多个第一电阻变化存储层中的每一个。

公开(公告)号：US07361554B2

公开(公告)日：2008-04-22

申请号：US11812574

申请日：2007-06-20

申请人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

发明人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

IPC分类号： H01L21/336

CPC分类号： H01L29/7926 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

摘要翻译： 公开了一种多位非易失性存储器件，其操作方法以及制造该多位非易失性存储器件的方法。 多位非易失性存储器件的单元可以形成在半导体衬底上，可以包括：垂直于半导体衬底的上表面设置的多个沟道; 多个存储节点，其设置在所述通道的相对侧，垂直于所述半导体衬底的上表面; 围绕通道和存储节点的上部以及存储节点的侧表面的控制门; 以及形成在通道和存储节点之间，通道和控制栅极之间以及存储节点和控制门之间的绝缘膜。

公开(公告)号：US07352037B2

公开(公告)日：2008-04-01

申请号：US11393750

申请日：2006-03-31

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  Eun-Hong Lee ,  Jae-woong Hyun ,  Jung-hoon Lee ,  Sung-jae Byun

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  Eun-Hong Lee ,  Jae-woong Hyun ,  Jung-hoon Lee ,  Sung-jae Byun

IPC分类号： H01L29/94

CPC分类号： H01L29/66795 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/11507 ,  H01L27/2436 ,  H01L29/785

摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.

摘要翻译： 半导体器件可以包括半导体衬底上的至少一对散热片。 可以在每个鳍中形成沟道区。 半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个 漏斗同时形成在相应的翅片上。

公开(公告)号：US08017991B2

公开(公告)日：2011-09-13

申请号：US11724290

申请日：2007-03-15

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L29/788

CPC分类号： H01L29/42352 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336

摘要： Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

摘要翻译： 示例性实施例提供了具有增加的集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括多个第一存储节点膜和半导体衬底上的多个第一控制栅电极。 多个第二存储节点膜和多个第二控制栅电极可以凹入到两个相邻的第一控制栅电极之间并且在多个第一控制栅电极的底部之下的半导体衬底中。 多个位线区域可以在半导体衬底上，并且每个可以跨越多个第一控制栅极电极和多个第二控制栅电极延伸。

公开(公告)号：US07700935B2

公开(公告)日：2010-04-20

申请号：US11882694

申请日：2007-08-03

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/24

摘要： A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 在非易失性存储器件中，第一导电类型的至少一个第一半导体层可以在衬底的一部分上彼此间隔开形成。 多个第一电阻变化存储层可以接触至少一个第一半导体层中的每一个的第一侧壁。 与第一导电类型相反的第二导电类型的多个第二半导体层可以插入在至少一个第一半导体层和多个第一电阻变化存储层中的每一个的第一侧壁之间。 多个位线电极可以连接到多个第一电阻变化存储层中的每一个。

公开(公告)号：US07560344B2

公开(公告)日：2009-07-14

申请号：US11976004

申请日：2007-10-19

申请人： Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

发明人： Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

公开(公告)号：US20090097321A1

公开(公告)日：2009-04-16

申请号：US12010943

申请日：2008-01-31

申请人： Suk-pil Kim ,  Yoon-dong Park ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee

发明人： Suk-pil Kim ,  Yoon-dong Park ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee

IPC分类号： G11C16/06 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833

摘要： A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.

摘要翻译： 非易失性存储器件可以包括至少一个半导体层，多个控制栅电极，多个电荷存储层，至少一个第一辅助电极和/或至少一个第二辅助电极。 多个控制栅电极可以凹入半导体层。 多个电荷存储层可以在多个控制栅电极和半导体层之间。 第一和第二辅助电极可以被布置成彼此面对。 多个控制栅电极可以在第一和第二辅助电极之间并与半导体层电容耦合。

公开(公告)号：US07492635B2

公开(公告)日：2009-02-17

申请号：US11371941

申请日：2006-03-10

申请人： Won-joo Kim ,  Yoon-dong Park

发明人： Won-joo Kim ,  Yoon-dong Park

IPC分类号： G11C11/34 ,  G11C11/00 ,  G11C16/04

CPC分类号： G11C11/5685 ,  G11C11/005 ,  G11C11/5621 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C16/04 ,  G11C2213/31 ,  H01L27/24 ,  H01L29/792

摘要： A hybrid multi-bit memory device may include a plurality of unit cells arranged in a matrix of a plurality of rows and columns. Each of the unit cells may include a first memory unit and a second memory unit. The first and second memory unit may share a source and a drain. The first memory unit of each unit cell arranged in each row may be connected to one of a plurality of word lines, and the drain of each unit cell arranged in each column may be connected to one of a plurality of bit lines.

摘要翻译： 混合多位存储器件可以包括以多个行和列的矩阵排列的多个单位单元。 每个单位单元可以包括第一存储器单元和第二存储器单元。 第一和第二存储器单元可以共享源极和漏极。 布置在每行中的每个单位单元的第一存储单元可以连接到多个字线中的一个，并且排列在每列中的每个单元的漏极可以连接到多个位线之一。

公开(公告)号：US20080191263A1

公开(公告)日：2008-08-14

申请号：US11980419

申请日：2007-10-31

申请人： Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Yoon-dong Park

发明人： Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Yoon-dong Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/7926

摘要： Provided are a nonvolatile memory device and a method of fabricating the same in which a channel length is effectively increased and high-integration may be possible. In the nonvolatile memory device, a semiconductor device may include an active region defined by a device isolation film. The active region may include at least one projecting portion. A pair of control gate electrodes may cover both side surfaces of the at least one projecting portion, and may be spaced apart from each other. A pair of charge storage layers may be between both side surfaces of the at least one projecting portion and the pair of control gate electrodes.

摘要翻译： 提供一种非易失性存储器件及其制造方法，其中沟道长度被有效地增加并且高集成度是可能的。 在非易失性存储器件中，半导体器件可以包括由器件隔离膜限定的有源区。 有源区域可以包括至少一个突出部分。 一对控制栅电极可以覆盖至少一个突出部分的两个侧表面，并且可以彼此间隔开。 一对电荷存储层可以位于至少一个突出部分的两个侧表面和一对控制栅极电极之间。

公开(公告)号：US20070284632A1

公开(公告)日：2007-12-13

申请号：US11709057

申请日：2007-02-22

申请人： Won-joo Kim ,  Yoon-dong Park ,  Jung-hoon Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  Jung-hoon Lee

IPC分类号： H01L29/00

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42332 ,  H01L29/792

摘要： A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.