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公开(公告)号：US20050184784A1
公开(公告)日：2005-08-25
申请号：US11043178
申请日：2005-01-27
IPC分类号： G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , G11C11/412 , G11C19/00 , H03K3/012 , H03K3/037 , H03K3/356 , H03K23/00 , H03K3/289
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.
摘要翻译： 锁存部分包括锁存电路。 锁存电路包括反相器并锁存来自门控部分的输入信号。 在锁存电路的一个反相器和输出端子OUT之间设置有根据复位信号的高/低切换开/关特性的模拟开关。 在输出端子和用于接收作为触发器的电源的低电位的输入端之间设置有根据复位信号的高/低切换开/关特性的开关元件。
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公开(公告)号：US20050179635A1
公开(公告)日：2005-08-18
申请号：US11053172
申请日：2005-02-09
申请人： Yuhichiroh Murakami , Hajime Washio
发明人： Yuhichiroh Murakami , Hajime Washio
CPC分类号： G09G3/3688 , G09G2310/0248
摘要： A driver circuit of a display apparatus is provided with a nor circuit in each output line of a timing pulse. To the nor circuit, inputted are a timing pulse to be supplied to the output line and a pre-charge pulse for pre-charging a data signal line SL to which a write signal is being inputted based on the timing pulse. With this structure, it is possible to realize a driver circuit storing a pre-charge circuit of a display apparatus, which can surely prevent a collision between a pre-charge potential and a potential of a video signal in a signal supply line when pre-charging the signal supply line from a pre-charge power supply of a small driving performance, while maintaining the number of stages in the shift register to be the required minimum number
摘要翻译： 显示装置的驱动器电路在定时脉冲的每个输出线中设置有电路。 输入到输出线路的定时脉冲，以及预充电脉冲，用于根据定时脉冲对输入写入信号的数据信号线SL进行预充电。 利用这种结构，可以实现一种存储显示装置的预充电电路的驱动电路，其可以可靠地防止预充电电位与信号供给线中的视频信号的电位之间的冲突， 从小型驾驶性能的预充电电源对信号电源线充电，同时将移位寄存器中的级数保持为所需的最小数量
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63.发明申请Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method 失效脉冲输出电路，显示装置的驱动电路和使用脉冲输出电路的显示装置，以及脉冲输出方式公开(公告)号：US20050134352A1
公开(公告)日：2005-06-23
申请号：US11002684
申请日：2004-12-03
CPC分类号： G09G3/3688 , G09G2310/0289 , G09G2310/0294
摘要： An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
摘要翻译： 触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。 然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。 此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。 通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从 多个输出端子。
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公开(公告)号：US20050088387A1
公开(公告)日：2005-04-28
申请号：US10941082
申请日：2004-09-15
CPC分类号： G09G3/3648 , G09G2310/0251 , G09G2310/0297 , G09G2320/0219
摘要： In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.
摘要翻译： 在每个水平周期中，通过仅在预定周期内同时分别为组中的R，G和B的三条数据信号线分别设置ON开关，将组中的数据信号线预先充电至预定电位 在数据信号提供期之前的同一时间。 在随后的数据信号供给周期中，对于R，G，B的数据信号线的各自的开关顺序地接通，顺序地向R，G，B的各个数据提供经选择的扫描信号线上的像素，经由数据信号 线条。 结果，在基于一组顺序提供的数据信号线的时分驱动的显示装置中，可以抑制显示时的上投电位波动。
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公开(公告)号：US20130002626A1
公开(公告)日：2013-01-03
申请号：US13583086
申请日：2011-04-07
申请人： Hajime Washio
发明人： Hajime Washio
CPC分类号： G09G3/2085 , G09G3/3614 , G09G3/3648 , G09G2300/0857 , G09G2330/021
摘要： An objective of the present invention is to provide a display device capable of reducing a circuit area on a panel substrate and realizing low power consumption by drive using memory.In a pixel memory portion of a display device, as corresponding to each pixel memory unit, there are provided a flip-flop (11), a voltage selection portion (12), which selects either white display voltage (VW) or black display voltage (VBL) in accordance with an output signal (Qn+1, Qn+1B) from the flip-flop (11), and a liquid crystal capacitance (13), which reflects the voltage selected by the voltage selection portion (12) in the display state of the pixel that corresponds to the flip-flop (11). Moreover, the flip-flops (11) respectively included in the pixel memory units within the pixel memory portion are connected in series, forming a shift register (110).
摘要翻译： 本发明的目的是提供一种能够减少面板基板上的电路面积并通过使用存储器的驱动实现低功耗的显示装置。 在显示装置的像素存储器部分中，对应于每个像素存储单元，设置有触发器（11），电压选择部分（12），其选择白色显示电压（VW）或黑色显示电压 根据来自触发器（11）的输出信号（Qn + 1，Qn + 1B）和液晶电容（13）反映由电压选择部分（12）选择的电压的液晶电容 对应于触发器（11）的像素的显示状态。 此外，分别包括在像素存储器部分内的像素存储器单元中的触发器（11）串联连接，形成移位寄存器（110）。
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66.发明授权Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method 失效脉冲输出电路，显示装置的驱动电路和使用脉冲输出电路的显示装置，以及脉冲输出方式公开(公告)号：US07786968B2
公开(公告)日：2010-08-31
申请号：US11002684
申请日：2004-12-03
IPC分类号： H03M1/50
CPC分类号： G09G3/3688 , G09G2310/0289 , G09G2310/0294
摘要： An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
摘要翻译： 触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。 然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。 此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。 通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从 多个输出端子。
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公开(公告)号：US07733321B2
公开(公告)日：2010-06-08
申请号：US11543219
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。
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公开(公告)号：US20090115716A1
公开(公告)日：2009-05-07
申请号：US11921116
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0232 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2340/0442 , G11C19/28
摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。
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公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
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公开(公告)号：US06996203B2
公开(公告)日：2006-02-07
申请号：US10860660
申请日：2004-06-04
IPC分类号： G11C19/00
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译： 本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出 预定阶段。
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