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130 条记录 (耗时 0.031 秒)

    Drive circuit
    61.
    发明授权
    Drive circuit 有权
    驱动电路

    公开(公告)号：US06791526B2

    公开(公告)日：2004-09-14

    申请号：US10097784

    申请日：2002-03-13

    申请人： Yasushi Kubota ,  Tatsumi Satoh

    发明人： Yasushi Kubota ,  Tatsumi Satoh

    IPC分类号： G09G336

    CPC分类号： G09G3/3685 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2310/06

    摘要： A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has the shifting direction of drive data sequentially shifted through shift registers (SR116-R60) and is further inverted by a control signal (SEL_SFT), and the data are shifted in the opposite direction, from the first shift register (SR61) to the second shift register (SR116). At this time, the upper group of switching circuits (SW1-SW56) or the lower group of switching circuits (SW116-SW61) is enabled and the other group is disabled by control signals (SEL_UP, SEL_LO). Once the drive data are shifted to the bits of the shift registers, a voltage selection signal generated by a decoder (DEn) is inputted to an output circuit via an effective switching circuit, and a drive signal for a TFT gate is outputted. The number of circuits is reduced because the shift registers (SR61-SR116) and decoders (DE61-DE116) are shared by two outputs.

    摘要翻译： 驱动电路，例如TFT液晶显示器的栅极线驱动电路，其电路尺寸比以往小。 TFT驱动电路具有通过移位寄存器（SR116-R60）顺序移位的驱动数据的移位方向，并且由控制信号（SEL_SFT）进一步反转，并且数据沿相反方向从第一移位寄存器（SR61 ）到第二移位寄存器（SR116）。 此时，开关电路（SW1-SW56）或下组开关电路（SW116-SW61）被使能，另一组被控制信号（SEL_UP，SEL_LO）禁止。 一旦驱动数据被移位到移位寄存器的位，由解码器（DEn）产生的电压选择信号通过有效的开关电路被输入到输出电路，并且输出用于TFT栅极的驱动信号。 由于移位寄存器（SR61-SR116）和解码器（DE61-DE116）由两个输出共享，所以电路数量减少。

    Liquid crystal display device
    63.
    发明授权
    Liquid crystal display device 有权
    液晶显示装置

    公开(公告)号：US06483495B2

    公开(公告)日：2002-11-19

    申请号：US09883263

    申请日：2001-06-19

    申请人： Yasuyoshi Kaise ,  Kenichi Ishiguro ,  Yasushi Kubota

    发明人： Yasuyoshi Kaise ,  Kenichi Ishiguro ,  Yasushi Kubota

    IPC分类号： G09G336

    CPC分类号： G02F1/13452 ,  G02F1/13454

    摘要： A liquid crystal display device comprises a base substrate including a display region, and a drive circuitry region provided in a surrounding region of the display region, a liquid crystal layer, and a counter substrate facing the base substrate via the liquid crystal layer. A pixel electrode and a pixel driving element for driving the pixel electrode are provided in the display region, a driving circuitry section for controlling the pixel electrode and the pixel driving element is provided in the drive circuitry region. An insulating layer is provided to cover at least one portion of the drive circuitry region. A common transition electrode is provided in the insulating layer. The common transition electrode is electrically connected to a counter electrode provided on the counter substrate.

    摘要翻译： 液晶显示装置包括：基板，包括显示区域;以及设置在显示区域的周围区域的驱动电路区域，液晶层，以及经由液晶层面向基板的对置基板。 用于驱动像素电极的像素电极和像素驱动元件设置在显示区域中，用于控制像素电极的驱动电路部分和像素驱动元件设置在驱动电路区域中。 提供绝缘层以覆盖驱动电路区域的至少一部分。 在绝缘层中设置公共的过渡电极。 公共过渡电极与设置在对置基板上的对电极电连接。

    Data signal line driving circuit and image display apparatus
    64.
    发明授权
    Data signal line driving circuit and image display apparatus 失效
    数据信号线驱动电路和图像显示装置

    公开(公告)号：US06437768B1

    公开(公告)日：2002-08-20

    申请号：US09060732

    申请日：1998-04-15

    申请人： Yasushi Kubota ,  Tamotsu Sakai ,  Ichiro Shiraki

    发明人： Yasushi Kubota ,  Tamotsu Sakai ,  Ichiro Shiraki

    IPC分类号： G09G336

    CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021

    摘要： A shift register circuit, composed of a plurality of serially connected latch circuits, for sequentially transmitting a pulse signal in sync with a rising and a falling of a clock signal, and an output circuit for sequentially outputting a video signal to data signal lines in sync with the pulse signal outputted from the shift register circuit are provided. The shift register circuit is divided into a plurality of latch circuit groups, and the stage numbers of the latch circuits in each latch circuit group is set in such a manner to minimize the time difference between the pulse signal outputted from each latch circuit group and the video signal outputted in sync with the pulse signal. Consequently, the power consumption on the clock signal lines can be reduced while the time difference between the clock signal and the video signal can be prevented, thereby making it possible to provide a data signal line driving circuit and an image forming display apparatus which can realize a display of a satisfactory image.

    摘要翻译： 一种移位寄存器电路，由多个串行连接的锁存电路组成，用于与时钟信号的上升和下降同步地顺序发送脉冲信号;以及输出电路，用于顺序地将数据信号线同步输出到数据信号线 提供从移位寄存器电路输出的脉冲信号。 移位寄存器电路被分成多个锁存电路组，并且每个锁存电路组中的锁存电路的级数被设定为使从每个锁存电路组输出的脉冲信号和 视频信号与脉冲信号同步输出。 因此，可以减少时钟信号线上的功耗，同时可以防止时钟信号和视频信号之间的时间差，从而可以提供数据信号线驱动电路和可以实现的图像形成显示装置 显示令人满意的图像。

    Logic circuit for liquid crystal display having pass-transistor logic circuitry and thin film transistors
    66.
    发明授权
    Logic circuit for liquid crystal display having pass-transistor logic circuitry and thin film transistors 失效
    具有传输晶体管逻辑电路和薄膜晶体管的液晶显示器的逻辑电路

    公开(公告)号：US5898322A

    公开(公告)日：1999-04-27

    申请号：US524503

    申请日：1995-09-07

    申请人： Yasushi Kubota ,  Hiroshi Yoneda

    发明人： Yasushi Kubota ,  Hiroshi Yoneda

    IPC分类号： G02F1/133 ,  G11C19/00 ,  H01L27/12 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/21 ,  H03K19/094 ,  H01L27/00

    CPC分类号： H03K19/215 ,  H03K19/1737

    摘要： A logic circuit performs a logic operation on a plurality of input logic signals and outputting a resultant logic signal. The logic circuit comprises a pass-transistor logic circuit including: a plurality of field effect transistors, at least two of the plurality of field effect transistors being coupled in series, a gate electrode of each of the at least two field effect transistors receiving a corresponding first logic signal, and one of drain and source electrodes ditto receiving a corresponding second logic signal; and a node for coupling the other of the drain and source electrodes of the at least two field effect transistors, and for outputting the resultant logic signal. The plurality of field effect transistors are thin film transistors (TFTs).

    摘要翻译： 逻辑电路对多个输入逻辑信号执行逻辑运算并输出合成的逻辑信号。 逻辑电路包括一个通过晶体管逻辑电路，包括：多个场效应晶体管，多个场效应晶体管中的至少两个串联耦合，所述至少两个场效应晶体管中的每一个的栅电极接收相应的 第一逻辑信号，以及漏极和源极之一，同时接收对应的第二逻辑信号; 以及用于耦合所述至少两个场效应晶体管的所述漏极和源极中的另一个的节点，并用于输出所得到的逻辑信号。 多个场效应晶体管是薄膜晶体管（TFT）。

    Thin-film transistor circuit and image display
    67.
    发明授权
    Thin-film transistor circuit and image display 失效
    薄膜晶体管电路和图像显示

    公开(公告)号：US5808595A

    公开(公告)日：1998-09-15

    申请号：US674601

    申请日：1996-06-28

    申请人： Yasushi Kubota ,  Masahiro Adachi ,  Hiromi Sakamoto ,  Narihiro Morosawa

    发明人： Yasushi Kubota ,  Masahiro Adachi ,  Hiromi Sakamoto ,  Narihiro Morosawa

    IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/78648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/043 ,  G09G2310/027

    摘要： A thin-film transistor circuit, which is used as a driving circuit for driving pixels in an image display, is constituted of a plurality of thin-film transistors that are formed on an insulating substrate. In each thin-film transistor, a conductive electrode is placed so as to face a gate electrode with a channel region of a polycrystal silicon thin-film that forms an active layer located in between. Here, a constant voltage is applied to the conductive electrode. When threshold voltage is shifted by applying a voltage to the conductive electrode, it is possible to allow the absolute value of the threshold voltage of n-channel-type transistors and the absolute value of the threshold voltage of p-channel-type transistors to become virtually equal to each other. Moreover, it is possible to properly set the threshold voltage in accordance with factors such as the channel length of the thin-film transistors, the types of circuits that are constituted of the thin-film transistors and voltages to be applied to the thin-film transistors. Thus, it becomes possible to remarkably improve the characteristics of thin-film transistor circuits, such as operation speeds and holding characteristics.

    摘要翻译： 作为用于驱动图像显示中的像素的驱动电路的薄膜晶体管电路由形成在绝缘基板上的多个薄膜晶体管构成。 在每个薄膜晶体管中，导电电极被放置成面对具有形成位于其间的有源层的多晶硅薄膜的沟道区的栅电极。 这里，向导电电极施加恒定电压。 当通过向导电电极施加电压来移动阈值电压时，可以允许n沟道型晶体管的阈值电压的绝对值和p沟道型晶体管的阈值电压的绝对值成为 几乎相等。 此外，可以根据诸如薄膜晶体管的沟道长度，由薄膜晶体管构成的电路的类型和施加到薄膜的电压等因素来适当地设置阈值电压 晶体管。 因此，可以显着提高诸如操作速度和保持特性的薄膜晶体管电路的特性。

    Method for judging the properties of molten cast iron
    68.
    发明授权
    Method for judging the properties of molten cast iron 失效
    判断熔融铸铁性能的方法

    公开(公告)号：US5804006A

    公开(公告)日：1998-09-08

    申请号：US643076

    申请日：1996-04-30

    申请人： Toshitake Kanno ,  Jun Iwahashi ,  Eiichi Sahara ,  Hidetaka Hiraoka ,  Mayuki Morinaka ,  Tsuneharu Sugie ,  Yasushi Kubota

    发明人： Toshitake Kanno ,  Jun Iwahashi ,  Eiichi Sahara ,  Hidetaka Hiraoka ,  Mayuki Morinaka ,  Tsuneharu Sugie ,  Yasushi Kubota

    IPC分类号： G01N25/06 ,  G01N25/04 ,  G01N33/20 ,  C21D1/54

    CPC分类号： G01N25/04 ,  G01N33/206

    摘要： A method for judging the properties of molten cast iron which consists of connecting three sampling vessels with an apparatus for obtaining a cooling curve of molten cast iron, measuring a cementite eutectic temperature (TEC) of cast iron poured to the first sampling vessel to which a chilling agent is contained, measuring a eutectic freezing temperature change of molten cast iron poured to the second sampling vessel being free of any additive, measuring a graphite eutectic temperature (TEG) of molten cast iron poured to the third sampling vessel, and inspecting a relation between the cementite eutectic temperature (TEC) and the graphite eutectic temperature (TEG) within the range of the eutectic freezing temperature change of molten cast iron.

    摘要翻译： 一种用于判断熔融铸铁性能的方法，该方法由连接三个采样容器的组件组成，用于获得熔融铸铁冷却曲线的装置，测量流入第一取样容器的铸铁的渗碳体共晶温度（TEC） 测量浇注到第二取样容器中的熔融铸铁的共熔冷冻温度变化，不含任何添加剂，测量浇注到第三取样容器的熔融铸铁的石墨共晶温度（TEG），并检查关系 在熔融铸铁的共晶冷冻温度变化范围内的渗碳体共晶温度（TEC）和石墨共晶温度（TEG）之间。

    Semiconductor memory device
    70.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5134588A

    公开(公告)日：1992-07-28

    申请号：US558328

    申请日：1990-07-27

    申请人： Yasushi Kubota ,  Katsuji Iguchi

    发明人： Yasushi Kubota ,  Katsuji Iguchi

    IPC分类号： G11C13/00

    CPC分类号： G11C13/00

    摘要： A semiconductor memory device of a type comprising a plurality of sense amplifiers of differential type arranged in one direction, a pair of bit lines extending outwardly from opposite sides of each of the sense amplifiers, a plurality of word lines extending in a direction intersecting the bit lines, and a memory cell disposed at each of intersecting points between the bit lines and the word lines. The device is characterized in that the memory cells which are connected respectively with the neighboring bit lines are connected with the different word lines. Therefore, not only can the interference noise between each bit-line pair be reduced, but also any possible erroneous operation can be eliminated, thereby increasing the data reading speed.

    摘要翻译： 一种类型的半导体存储器件，包括沿一个方向布置的多个差分型读出放大器，从每个读出放大器的相对侧向外延伸的一对位线，沿与该位相交的方向延伸的多个字线 线，以及设置在位线和字线之间的交点处的存储单元。 该装置的特征在于分别与相邻位线连接的存储单元与不同的字线连接。 因此，不仅可以减少每个位线对之间的干扰噪声，而且可以消除任何可能的错误操作，从而增加数据读取速度。