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79 条记录 (耗时 0.038 秒)

    Charging device
    62.
    发明授权
    Charging device 失效
    充电装置

    公开(公告)号：US4851960A

    公开(公告)日：1989-07-25

    申请号：US131585

    申请日：1987-12-11

    申请人： Shunji Nakamura ,  Hiromitsu Hirabayashi ,  Junji Araya ,  Noribumi Koitabashi

    发明人： Shunji Nakamura ,  Hiromitsu Hirabayashi ,  Junji Araya ,  Noribumi Koitabashi

    IPC分类号： G03G15/02

    CPC分类号： G03G15/0216

    摘要： A charging device for contact-charging a member to be charged. A charging device for charging a movable member to be charged includes a contacting member adapted to contacting the member to be charged, and means for forming a vibratory electric field between the member to be charged and the contacting member, the vibratory electric field forming means applying between the members a vibratory voltage having a peak-to-peak value not less than twice an absolute value of charge starting voltage to the member to be charged. The member to be charged can be uniformly charged.

    Movable device
    63.
    发明授权
    Movable device 有权
    活动装置

    公开(公告)号：US07602097B2

    公开(公告)日：2009-10-13

    申请号：US12237681

    申请日：2008-09-25

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H02N2/00

    CPC分类号： B81B3/0059 ,  B81B2201/018 ,  B81B2201/047 ,  B81B2203/0109 ,  B81B2203/0181 ,  B81B2203/053 ,  B81B2203/055 ,  B81B2203/056 ,  B81B2203/058

    摘要： A movable device simultaneously enabling reduction of size down to the submicron level, higher speed operation, a streamlined production process, low costs, and greater reliability. A movable device provided with bottom electrodes and a basic conductive layer fixed to a substrate, an elastic shaft of a carbon nanotube with a bottom end fixed on the basic conductive layer and standing up, and a top structure including a top electrode spaced away from the bottom electrode and fixed to a top end of the elastic shaft, wherein when applying voltage between a bottom electrode and the top electrode, the top electrode displaces relatively to the bottom electrodes within an allowable range of elastic deformation of the elastic shaft.

    摘要翻译： 可移动装置同时能够将尺寸减小到亚微米级，更高的速度操作，简化的生产过程，低成本和更高的可靠性。 一种可移动装置，其具有底部电极和固定在基板上的基本导电层，碳纳米管的弹性轴，其底端固定在基本导电层上并竖立起来，顶部结构包括顶部电极， 底部电极并固定到弹性轴的顶端，其中当在底部电极和顶部电极之间施加电压时，顶部电极在弹性轴的弹性变形的允许范围内相对于底部电极移位。

    Semiconductor device and method for fabricating the same
    64.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07166882B2

    公开(公告)日：2007-01-23

    申请号：US10095101

    申请日：2002-03-12

    申请人： Shunji Nakamura ,  Eiji Yoshida

    发明人： Shunji Nakamura ,  Eiji Yoshida

    IPC分类号： H01L31/119

    CPC分类号： H01L27/10852 ,  H01L21/7682 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device comprises: an insulation film 72 formed over a silicon substrate 10, an insulation film 78 formed on the insulation film 72 and having opening 82, and conductor 84 formed at least in the opening 82. Cavity 88 having the peripheral edges conformed to a configuration of the opening 82 is formed in the insulation film 72. The cavity 88 is formed in the region between the electrodes or the regions between the interconnection layers so as to decrease the dielectric constant between the electrodes or between the interconnection layers, whereby the parasitic capacitances of the region between the electrodes or the region between the interconnection layers can be drastically decreased, and consequently the semiconductor device can have higher speed.

    摘要翻译： 半导体器件包括：形成在硅衬底10上的绝缘膜72，形成在绝缘膜72上并具有开口82的绝缘膜78和至少形成在开口82中的导体84。 在绝缘膜72上形成具有与开口82的构造一致的周缘的腔88。 空腔88形成在电极之间的区域或互连层之间的区域中，以便降低电极之间或互连层之间的介电常数，由此电极之间的区域或互连层之间的区域的寄生电容 层可以大大降低，因此半导体器件可以具有更高的速度。

    Semiconductor memory device and method for fabricating the same
    65.
    发明申请
    Semiconductor memory device and method for fabricating the same 失效

    公开(公告)号：US20060084226A1

    公开(公告)日：2006-04-20

    申请号：US11248136

    申请日：2005-10-13

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10873 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/945

    摘要： A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

    Semiconductor device with wiring embedded in trenches and vias
    66.
    发明授权
    Semiconductor device with wiring embedded in trenches and vias 失效
    具有布线的半导体器件嵌入沟槽和通孔中

    公开(公告)号：US06856024B2

    公开(公告)日：2005-02-15

    申请号：US10376308

    申请日：2003-03-03

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/10852 ,  H01L21/76816 ,  H01L27/10814 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film. With this method, an opening having different cross sectional shapes at different depths can be formed with a smaller number of masks.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底上形成层间绝缘膜; （b）在所述层间绝缘膜上形成第一掩模，所述第一掩模具有与第一方向平行的多个条纹图案，并从所述层间绝缘膜的表面蚀刻到第一中间深度以形成沟槽; 和（c）在所述层间绝缘膜上形成第二掩模，所述第二掩模具有平行于与所述第一方向交叉的第二方向的多个条纹图案，并且在与所述第二掩模相对应的区域中蚀刻所述层间绝缘膜的剩余厚度 并且不被第二掩模覆盖以形成开口，并且在除了与凹槽相对应的区域之外的区域中以形成从层间绝缘膜的表面到达第二中间深度的第二槽。 利用这种方法，可以用较少数量的掩模形成在不同深度处具有不同横截面形状的开口。

    Semiconductor device and method for fabricating the same
    67.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06576527B2

    公开(公告)日：2003-06-10

    申请号：US08965010

    申请日：1997-11-05

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H01L2120

    CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

    摘要： The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

    摘要翻译： 在半导体衬底10上包括存储单元区域和外围电路区域的半导体器件包括形成在存储单元区域中的转移晶体管，由与转移晶体管的扩散层20之一连接的存储电极46构成的电容器，形成 第一导电层，覆盖存储电极46的侧壁的电介质膜52和形成在电介质膜52上的相对电极56; 由第一导电层形成并连接到半导体衬底10的外围电路区域的导电插头; 以及电连接到导电插头48的第一互连62。

    Method for fabricating a semiconductor memory device
    68.
    发明授权
    Method for fabricating a semiconductor memory device 失效
    半导体存储器件的制造方法

    公开(公告)号：US5776789A

    公开(公告)日：1998-07-07

    申请号：US660324

    申请日：1996-06-04

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L21/70

    CPC分类号： H01L27/10873 ,  H01L21/84 ,  H01L27/1082 ,  H01L27/1203 ,  Y10S148/014 ,  Y10S148/135 ,  Y10S438/977

    摘要： A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

    摘要翻译： 半导体存储器件包括具有形成在其中的第一扩散区域和第二扩散区域的硅层，在第一和第二扩散区域之间的硅层的一侧上通过绝缘膜形成的栅电极，形成在所述第一扩散区域上的电容器 硅层的一侧并具有连接到第一扩散区的存储电极，以及形成在硅层的另一侧并连接到第二扩散区的位线，由此SOI结构的半导体存储器件可以容易地 制造。 连接到第二扩散区的位线形成在半导体层的另一侧，由此可以不受限于电容器的结构等而排列位线。 可以防止电容器和位线之间的短路。

    Bipolar transistor having ring shape base and emitter regions
    69.
    发明授权
    Bipolar transistor having ring shape base and emitter regions 失效
    具有环形基极和发射极区域的双极晶体管

    公开(公告)号：US5712505A

    公开(公告)日：1998-01-27

    申请号：US569942

    申请日：1995-12-08

    申请人： Shunji Nakamura

    发明人： Shunji Nakamura

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L29/70 ,  H01L29/739

    CPC分类号： H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

    摘要： A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer. On the other hand, in a region surrounded by the ring-shaped base region in which the ring-shaped emitter region is formed a little toward the outer periphery, a conductive layer is laminated through an insulating layer, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped base region and the conductive layer are connected through the conductive side wall. A metallic base electrode is connected to the conductive layer. Since an emitter region and a collector region have the same conduction type in a bipolar transistor, such a bipolar transistor that has a construction in which the emitter described above is used as a collector is also available.

    摘要翻译： 在双极型晶体管的环状基极区域的上层部分的内周部分或稍微朝向外周的区域中形成环状发射极区域。 导电层通过绝缘层层叠在由基部区域的内周稍微设置的环状发射极区域围绕的区域中，在导电层和绝缘层的侧面形成导电性侧壁， 并且环形发射极区域和导电层通过导电侧壁连接。 金属发射极连接到导电层。 另一方面，在由环状的发射极区域朝向外周形成一点的环状基极区域围绕的区域中，导电层通过绝缘层层叠，导电侧壁形成在 导电层和绝缘层的侧面以及环状基极区域和导电层通过导电侧壁连接。 金属基极连接到导电层。 由于发射极区域和集电极区域在双极晶体管中具有相同的导电类型，所以具有其中使用上述发射极的结构的双极晶体管也可用作集电极。