公开(公告)号：US07405438B2

公开(公告)日：2008-07-29

申请号：US10945774

申请日：2004-09-20

申请人： Shenlin Chen ,  Trung Tri Doan ,  Guy T. Blalock ,  Lyle D. Breiner ,  Er-Xuan Ping

发明人： Shenlin Chen ,  Trung Tri Doan ,  Guy T. Blalock ,  Lyle D. Breiner ,  Er-Xuan Ping

IPC分类号： H01L29/72

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

摘要翻译： 本发明包括形成坚固的含半导体的表面的方法。 在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。 随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。 将种子退火以形成坚固的含半导体的表面。 第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。 本发明还包括包括粗糙表面的半导体结构。 坚固的表面可以是例如坚固的硅。

公开(公告)号：US07355232B2

公开(公告)日：2008-04-08

申请号：US11218578

申请日：2005-09-06

申请人： Er-Xuan Ping ,  Shenlin Chen

发明人： Er-Xuan Ping ,  Shenlin Chen

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10885 ,  H01L28/84 ,  H01L28/91

摘要： A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

摘要翻译： 公开了双面HSG电容器和制造方法。 作为双面下电容器电极的一部分，在掺杂多晶层和半球状多晶硅层（HSG）之间形成薄的自然氧化物层。 在电介质形成之前，下部电容器电极可以任选退火以改善电容。

公开(公告)号：US07344755B2

公开(公告)日：2008-03-18

申请号：US10646673

申请日：2003-08-21

申请人： Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

发明人： Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

IPC分类号： C23C16/00

CPC分类号： C23C16/45546 ,  C23C16/4404

摘要： The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.

摘要翻译： 本公开提供了可用于处理微特征工件（例如半导体晶片）的方法和装置。 一些方面在分批过程中沉积TiN具有特殊的用途。 一个实施方案包括通过同时引入第一和第二预处理前体（例如，TiCl 4和NH 3）来预处理处理室的表面，以将预处理材料沉积在室表面上 。 在预处理之后，可以将第一微特征工件放置在腔室中，并且可以通过交替地引入量的第一和第二沉积前体将TiN沉积在微特征工件上。

公开(公告)号：US07235138B2

公开(公告)日：2007-06-26

申请号：US10646607

申请日：2003-08-21

申请人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

发明人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

IPC分类号： C23C16/00 ,  H01L21/306 ,  C23F1/00

CPC分类号： C23C16/4583 ,  C23C16/45546 ,  C23C16/45578 ,  Y10S206/832

摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

摘要翻译： 本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。 这些设备中的一些包括微型工件保持器，其包括气体分配器。 一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。 该工件保持器包括多个工件支撑件和气体分配器。 工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。 气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

公开(公告)号：US20060213440A1

公开(公告)日：2006-09-28

申请号：US11430328

申请日：2006-05-09

申请人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

发明人： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  David Kubista ,  Cem Basceri

IPC分类号： C23C16/00

CPC分类号： C23C16/45546 ,  C23C16/45578 ,  C23C16/4583

摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

公开(公告)号：US20060205142A1

公开(公告)日：2006-09-14

申请号：US11375696

申请日：2006-03-13

申请人： Er-Xuan Ping ,  Zhiping Yin

发明人： Er-Xuan Ping ,  Zhiping Yin

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L21/8242

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/84 ,  H01L28/91 ,  H01L29/945

摘要： The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

摘要翻译： 本发明包括形成氮化硅层的方法。 提供了包括第一质量和第二质量的衬底。 第一质量包括硅，第二质量包含氧化硅。 在第一质量块上形成牺牲层。 当牺牲层超过第一质量时，在第二质量块上形成含氮材料。 在形成含氮材料之后，去除牺牲层。 随后，形成氮化硅层以跨越第一和第二质量块延伸，其中氮化硅层在含氮材料之上。 此外，在第一质量块内提供导电性增强掺杂剂。 本发明还涉及形成电容器结构的方法。

公开(公告)号：US20060204649A1

公开(公告)日：2006-09-14

申请号：US11418337

申请日：2006-05-04

申请人： Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

发明人： Kevin Beaman ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Er-Xuan Ping ,  David Kubista ,  Cem Basceri ,  Lingyi Zheng

IPC分类号： C23C16/00 ,  C23C16/52

CPC分类号： C23C16/00 ,  C23C16/46

摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

摘要翻译： 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US07056806B2

公开(公告)日：2006-06-06

申请号：US10665099

申请日：2003-09-17

申请人： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

发明人： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

IPC分类号： H01L21/76 ,  H01L21/20 ,  H01L21/36 ,  H01L21/04 ,  H01L21/261

CPC分类号： C23C16/45527 ,  C23C16/34 ,  C23C16/45546

摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

公开(公告)号：US20060003512A1

公开(公告)日：2006-01-05

申请号：US11204806

申请日：2005-08-15

申请人： Fernando Gonzalez ,  Er-Xuan Ping

发明人： Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8238

CPC分类号： H01L27/10894 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/933

摘要： The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

摘要翻译： 本发明包括形成半导体电路的方法。 提供单晶硅衬底，并且形成覆盖衬底的第一部分并且留下未覆盖的第二部分的掩模。 在未覆盖部分中形成沟槽，并且至少部分地填充有半导体材料，该半导体材料包括除硅以外的元素的至少一个原子百分比。 去除掩模，并且在衬底的第一部分上形成第一半导体电路部件。 此外，第二半导体电路部件形成在至少部分地填充沟槽的半导体材料之上。 本发明还包括半导体结构。

公开(公告)号：US20060001066A1

公开(公告)日：2006-01-05

申请号：US11203046

申请日：2005-08-12

申请人： Er-Xuan Ping ,  Zhiping Yin

发明人： Er-Xuan Ping ,  Zhiping Yin

IPC分类号： H01L31/119 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/84 ,  H01L28/91 ,  H01L29/945

摘要： The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

摘要翻译： 本发明包括形成氮化硅层的方法。 提供了包括第一质量和第二质量的衬底。 第一质量包括硅，第二质量包含氧化硅。 在第一质量块上形成牺牲层。 当牺牲层超过第一质量时，在第二质量块上形成含氮材料。 在形成含氮材料之后，去除牺牲层。 随后，形成氮化硅层以跨越第一和第二质量块延伸，其中氮化硅层在含氮材料之上。 此外，在第一质量块内提供导电性增强掺杂剂。 本发明还涉及形成电容器结构的方法。