公开(公告)号：US6165861A

公开(公告)日：2000-12-26

申请号：US152348

申请日：1998-09-14

申请人： Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

发明人： Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.

摘要翻译： 通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。 电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。 图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。 形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。 盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。 沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。 未反应的金属被蚀刻。 沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。 沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。 金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。 在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

公开(公告)号：US08921934B2

公开(公告)日：2014-12-30

申请号：US13546738

申请日：2012-07-11

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC分类号： H01L29/66

CPC分类号： H01L29/401 ,  H01L29/0684 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66704 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7856

摘要： An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

摘要翻译： 一种集成电路器件包括：衬垫层，其具有主体部分，该主体部分具有横向邻近具有第二掺杂类型的漂移区域部分的第一掺杂型，形成在焊盘层中的沟槽，沟槽延伸穿过主体部分的界面和 漂移区部分，形成在沟槽中的栅极和沿着主体部分和漂移区部分的界面的焊盘层的顶表面上的栅极，形成在栅极的相对侧上的沟槽中的氧化物和嵌入的场板 在栅极的每个相对侧上的氧化物中。

公开(公告)号：US08884369B2

公开(公告)日：2014-11-11

申请号：US13486633

申请日：2012-06-01

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/823425 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7827 ,  H01L29/7831

摘要： A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.

摘要翻译： 一种器件包括第一导电类型的半导体层以及半导体层上的第一和第二体区，其中第一和第二体区具有与第一导电类型相反的第二导电类型。 第一导电类型的掺杂半导体区域设置在第一和第二主体区域之间并且与第一和第二主体区域接触。 栅极电介质层设置在第一和第二主体区域和掺杂半导体区域上。 第一和第二栅极设置在栅极介电层上方，分别与第一和第二体区重叠。 第一和第二栅电极在物理上彼此分开一个空间，并被电互连。 第一和第二栅电极之间的空间与掺杂半导体区域重叠。

公开(公告)号：US08823096B2

公开(公告)日：2014-09-02

申请号：US13486768

申请日：2012-06-01

申请人： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chun-Wai Ng

发明人： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chun-Wai Ng

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/30604 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/7827 ,  H01L29/7833

摘要： A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.

摘要翻译： 一种器件包括半导体芯片中的半导体区域，半导体区域上的栅极电介质层和栅极电介质上的栅电极。 漏极区域设置在半导体区域的顶表面并与栅电极相邻。 栅极间隔物位于栅电极的侧壁上。 电介质层设置在栅电极和栅间隔物上。 导电场板在电介质层的上方，其中导电场板具有在栅电极的漏极侧的一部分。 深金属通孔设置在半导体区域中。 源电极位于半导体区域的下方，其中源电极通过深金属通孔与导电场板电短路。

公开(公告)号：US08786050B2

公开(公告)日：2014-07-22

申请号：US13100714

申请日：2011-05-04

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

公开(公告)号：US08507988B2

公开(公告)日：2013-08-13

申请号：US12792055

申请日：2010-06-02

申请人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

发明人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66689

摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

摘要翻译： 高压（HV）器件包括在衬底上的栅极电介质结构。 栅介质结构具有第一部分和第二部分。 第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。 第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。 第一厚度大于第二厚度。 栅电极设置在栅介电结构上。 一个金属层结合在栅电极上。 金属层沿栅极电介质结构下方的沟道的方向延伸。 至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

公开(公告)号：US20130181285A1

公开(公告)日：2013-07-18

申请号：US13351295

申请日：2012-01-17

申请人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

发明人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

摘要翻译： 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

公开(公告)号：US20130134512A1

公开(公告)日：2013-05-30

申请号：US13348463

申请日：2012-01-11

申请人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

摘要： A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate

摘要翻译： 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上

公开(公告)号：US20110220995A1

公开(公告)日：2011-09-15

申请号：US12721045

申请日：2010-03-10

申请人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

发明人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

公开(公告)号：US20100219463A1

公开(公告)日：2010-09-02

申请号：US12699397

申请日：2010-02-03

申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao Chin Tuan

发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao Chin Tuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7809

摘要： A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

摘要翻译： 半导体器件提供高击穿电压和低导通电阻。 该装置包括：基板; 埋设在衬底中的n +层; 设置在掩埋的n +层上的n外延层; 设置在n外延层中的p阱; 源极n +区域，设置在p阱中并连接到一侧的源极触点; 设置在p阱和n外延层顶部的第一绝缘层; 设置在所述第一绝缘层的顶部上的栅极; 以及从掩埋n +层延伸到漏极接触的金属电极，其中金属电极通过第二绝缘层与n外延层和p阱绝缘。