公开(公告)号：US08575584B2

公开(公告)日：2013-11-05

申请号：US13225431

申请日：2011-09-03

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L29/02

CPC分类号： H01L27/101 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively.

摘要翻译： 本发明涉及结合有垂直选择晶体管的电阻式存储器件及其制造方法。 电阻式存储器件包括具有第一类型导电性的半导体衬底; 多个垂直选择晶体管，形成在阵列中的半导体衬底上，多个垂直选择晶体管中的每一个包括从半导体衬底突出的半导体柱，半导体柱的顶部区域具有与第一类型导电性相反的第二类型导电性 设置在半导体衬底中; 以及围绕所述半导体柱的栅电极，其间插入有栅极电介质层，所述栅电极的高度低于所述半导体柱; 设置在垂直选择晶体管顶部的多个接触柱; 设置在接触柱顶部的多个电阻性存储元件; 多个并行字线，通过相应的栅电极连接垂直选择晶体管，并行字线沿着第一方向延伸; 连接所述电阻性存储器元件的多条并行位线，所述并行位线沿着与所述并行字线中设置的第一方向不同的第二方向延伸; 以及在半导体柱的行之间分别形成有在半导体衬底的顶部区域中的具有第二类型导电体的多条平行的源极线，其中半导体柱的源极线和顶部区域分别用作源极和漏极。

公开(公告)号：US20130126823A1

公开(公告)日：2013-05-23

申请号：US13356633

申请日：2012-01-23

申请人： Kimihiro SATOH ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro SATOH ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L47/00 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

摘要翻译： 本发明涉及其中结合有新颖的存储单元架构的存储器件，其包括共享公共通道的选择晶体管阵列及其制造方法。 存储器件包括具有第一类型导电性的半导体衬底，多个漏极区域和由衬底中的公共板沟道分开的公共源极区域，以及选择栅极，其设置在板沟道的顶部，栅极介电层插入 之间。 多个漏极区域和公共源极区域具有与设置在衬底中的第一类型相反的第二类型导电性。

公开(公告)号：US20130075840A1

公开(公告)日：2013-03-28

申请号：US13369756

申请日：2012-02-09

申请人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

发明人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L43/12

摘要： A self-aligned via of a MRAM cell that connects a memory element including a top electrode, a memory element stack having a plurality of layers, and a bottom electrode to a bit line running over array of the memory elements. The self-aligned via also serves as a hard mask for memory element etching. The hard mask material has high selectivity in the etching ambient to maintain enough remaining thickness. It is also selectively removed during dual damascene process to form a self-aligned via hole. In one embodiment, Aluminum oxide or Magnesium oxide is adapted as the hard mask.

摘要翻译： 将包括顶部电极，具有多个层的存储元件堆叠和底部电极的存储元件连接到存储元件的阵列上的位线的MRAM单元的自对准通孔。 自对准通孔也用作记忆元件蚀刻的硬掩模。 硬掩模材料在蚀刻环境中具有高选择性以保持足够的剩余厚度。 还可以在双镶嵌工艺中选择性地去除以形成自对准的通孔。 在一个实施方案中，氧化铝或氧化镁适合作为硬掩模。

公开(公告)号：US20130032775A1

公开(公告)日：2013-02-07

申请号：US13317564

申请日：2011-10-20

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L45/00

CPC分类号： H01L23/5226 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

公开(公告)号：US07916433B2

公开(公告)日：2011-03-29

申请号：US12816108

申请日：2010-06-15

申请人： Yiming Huai ,  Zhitao Diao ,  Eugene Youjun Chen

发明人： Yiming Huai ,  Zhitao Diao ,  Eugene Youjun Chen

IPC分类号： G11B5/127 ,  G11C11/14

CPC分类号： G11B5/3909 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3906 ,  G11C11/161 ,  H01L43/10 ,  Y10T428/115

摘要： A method and system for providing a magnetic element are described. The method and system include providing a pinned layer, a barrier layer, and a free layer. The free layer includes a first ferromagnetic layer, a second ferromagnetic layer, and an intermediate layer between the first ferromagnetic layer and the second ferromagnetic layer. The barrier layer resides between the pinned layer and the free layer and includes MgO. The first ferromagnetic layer resides between the barrier layer and the intermediate layer. The first ferromagnetic layer includes at least one of CoFeX and CoNiFeX, with X being selected from the group of B, P, Si, Nb, Zr, Hf, Ta, Ti, and being greater than zero atomic percent and not more than thirty atomic percent. The first ferromagnetic layer is ferromagnetically coupled with the second ferromagnetic layer. The intermediate layer is configured such that the first ferromagnetic layer has a first crystalline orientation and the second ferromagnetic layer has a second crystalline orientation different from the first ferromagnetic layer.

摘要翻译： 描述了一种用于提供磁性元件的方法和系统。 该方法和系统包括提供钉扎层，阻挡层和自由层。 自由层包括第一铁磁层，第二铁磁层和第一铁磁层与第二铁磁层之间的中间层。 阻挡层位于被钉扎层和自由层之间，并且包括MgO。 第一铁磁层位于阻挡层和中间层之间。 第一铁磁层包括CoFeX和CoNiFeX中的至少一种，其中X选自B，P，Si，Nb，Zr，Hf，Ta，Ti，并且大于零原子百分比且不超过三十个原子 百分。 第一铁磁层与第二铁磁层铁磁耦合。 中间层被配置为使得第一铁磁层具有第一结晶取向，而第二铁磁层具有不同于第一铁磁层的第二晶体取向。

公开(公告)号：US07821087B2

公开(公告)日：2010-10-26

申请号：US11685723

申请日：2007-03-13

申请人： Paul Nguyen ,  Yiming Huai ,  Zhitao Diao ,  Frank Albert

发明人： Paul Nguyen ,  Yiming Huai ,  Zhitao Diao ,  Frank Albert

IPC分类号： H01L29/82

CPC分类号： H01L43/10 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/16 ,  H01F10/3263 ,  H01F10/3272 ,  H01F41/303

摘要： A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. In one aspect, the free layer(s) include ferromagnetic material(s) diluted with nonmagnetic material(s) and/or ferrimagnetically doped to provide low saturation magnetization(s).

摘要翻译： 公开了一种用于提供可用于磁存储器中的磁性元件的方法和系统。 磁性元件包括固定，非磁性间隔物和自由层。 间隔层位于固定层和自由层之间。 当写入电流通过磁性元件时，可以使用自旋转移来切换自由层。 磁性元件还可以包括阻挡层，第二被钉扎层。 或者，包括第二固定和第二间隔层和静电耦合到自由层的第二自由层。 在一个方面，自由层包括用非磁性材料稀释的铁磁材料和/或亚铁磁掺杂以提供低的饱和磁化强度。

公开(公告)号：US07576956B2

公开(公告)日：2009-08-18

申请号：US11190255

申请日：2005-07-26

申请人： Yiming Huai

发明人： Yiming Huai

IPC分类号： G11B5/39

CPC分类号： G11C11/16 ,  G01R33/06 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic or magnetoresistive tunnel junctions (MTJs) having diffusion stop layers to eliminate or reduce diffusion of oxygen, nitrogen or other particles from the barrier layer to the ferromagnetic layers during the film deposition process including the barrier oxidation or nitridation process and the post annealing process. Such MTJs may be used in various applications including magnetic memory (MRAM) devices and magnetic recording heads.

摘要翻译： 磁阻或磁阻隧道结（MTJ）具有扩散停止层，以消除或减少包括阻挡氧化或氮化过程和后退火过程的膜沉积过程中氧，氮或其他颗粒从阻挡层到铁磁层的扩散。 这样的MTJ可以用于包括磁存储器（MRAM）装置和磁记录头的各种应用中。

公开(公告)号：US07531882B2

公开(公告)日：2009-05-12

申请号：US11239969

申请日：2005-09-30

申请人： Paul P. Nguyen ,  Yiming Huai

发明人： Paul P. Nguyen ,  Yiming Huai

IPC分类号： H01L43/00

CPC分类号： H01F41/302 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/093 ,  G01R33/1284 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/30 ,  H01F10/3236 ,  H01F10/3263 ,  H01F10/3272 ,  H01F10/3286 ,  H01L43/08 ,  Y10T428/26 ,  Y10T428/261 ,  Y10T428/265

摘要： A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. At least one free layer has a high perpendicular anisotropy. The high perpendicular anisotropy has a perpendicular anisotropy energy that is at least twenty and less than one hundred percent of the out-of-plane demagnetization energy.

摘要翻译： 公开了一种用于提供可用于磁存储器中的磁性元件的方法和系统。 磁性元件包括固定，非磁性间隔物和自由层。 间隔层位于固定层和自由层之间。 当写入电流通过磁性元件时，可以使用自旋转移来切换自由层。 磁性元件还可以包括阻挡层，第二被钉扎层。 或者，包括第二固定和第二间隔层和静电耦合到自由层的第二自由层。 至少一个自由层具有高的垂直各向异性。 高垂直各向异性具有垂直各向异性能，其至少为平面外退磁能的百分之二十。

公开(公告)号：US07489541B2

公开(公告)日：2009-02-10

申请号：US11210452

申请日：2005-08-23

申请人： Mahendra Pakala ,  Eugene Youjun Chen ,  Yiming Huai

发明人： Mahendra Pakala ,  Eugene Youjun Chen ,  Yiming Huai

IPC分类号： G11C11/00

CPC分类号： H01L43/08 ,  B82Y25/00 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3259 ,  H01F10/3263 ,  H01F10/3272 ,  H01F10/3281 ,  H01L43/10

摘要： A method and system for providing a magnetic element are disclosed. The method and system include providing a pinned layer, providing a spacer layer, and providing a free layer. The free layer is ferrimagnetic and includes at least one of a conductive ferrite, a garnet, a ferrimagnetic alloy excluding a rare earth, a heavy rare-earth-transition metal alloy, a half-metallic ferrimagnetic, and a bilayer. The bilayer includes a rare earth-transition metal alloy layer and a spin current enhancement layer. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.

摘要翻译： 公开了一种用于提供磁性元件的方法和系统。 该方法和系统包括提供钉扎层，提供间隔层，并提供自由层。 自由层是亚铁磁性的，并且包括导电铁氧体，石榴石，除稀土之外的亚铁磁合金，重稀土 - 过渡金属合金，半金属亚铁磁性和双层中的至少一种。 双层包括稀土 - 过渡金属合金层和自旋电流增强层。 磁性元件配置成当写入电流通过磁性元件时由于自旋转移而允许自由层被切换。

公开(公告)号：US20080310213A1

公开(公告)日：2008-12-18

申请号：US11764057

申请日：2007-06-15

申请人： Eugene Chen ,  Yiming Huai ,  Alexander A.G. Driskill-Smith

发明人： Eugene Chen ,  Yiming Huai ,  Alexander A.G. Driskill-Smith

IPC分类号： G11C11/02 ,  G11C11/40 ,  H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  Y10S977/935

摘要： A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

摘要翻译： 描述了包含该单元的磁存储单元和磁存储器。 磁存储单元包括至少一个磁性元件和至少一个非平面选择装置。 磁性元件可通过驱动通过磁性元件的写入电流来编程。 磁存储器可以包括多个磁存储单元，对应于多个磁存储单元的多个位线，以及对应于多个磁存储单元的多个源极线。