公开(公告)号：US11947471B2

公开(公告)日：2024-04-02

申请号：US17852135

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

CPC classification number: G06F13/1626 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US20240103758A1

公开(公告)日：2024-03-28

申请号：US18367241

申请日：2023-09-12

Applicant: Rambus Inc.

Inventor： J. James TRINGALI

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0608 ,  G06F3/0679

Abstract: A buffer/interface device of the memory node may read and compress blocks of data (e.g., pages). When a memory buffer device compresses a block of data, it may keep storing the original uncompressed version in the original memory location (e.g., physical memory page). In this manner, an access directed to the block of data may be satisfied with the uncompressed version retrieved from the original memory location (e.g., physical memory page) without having to perform a decompression operation. As memory space is needed for other purposes (e.g., for an uncompressed copy of a recently decompressed block or as host allocated memory occupies more space), the original uncompressed versions of blocks (pages) that have not been accessed relatively recently (e.g., relative to other kept original uncompressed versions) may be evicted and replaced by other blocks of data (e.g., either compressed or uncompressed).

公开(公告)号：US20240097880A1

公开(公告)日：2024-03-21

申请号：US18039865

申请日：2021-11-30

Applicant: RAMBUS INC.

Inventor： Pascal VAN LEEUWEN

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: Disclosed embodiments relate to cipher accelerator circuit comprising: a first affine transformation circuit generating a first data block from an input data block, a SM4 S-box circuit configured to perform a first byte S-box operation according to a SM4 cipher and using a SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substituted data block; and a second affine transformation circuit generating a second data block from the substituted data block, wherein the first and second affine transformation circuits are configured to perform multiplication of the substituted data block by a respective matrix and addition of a respective translation vector, and wherein the first and second affine transformations circuits are configured such that the second transformed data block is equal to the input data block processed by a second S-box operation according to another symmetric cipher using S-box tables.

公开(公告)号：US20240078044A1

公开(公告)日：2024-03-07

申请号：US18371300

申请日：2023-09-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/4282

Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.

公开(公告)号：US11922066B2

公开(公告)日：2024-03-05

申请号：US17576529

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Raymond Miller ,  Steven C. Woo

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/1006

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.

公开(公告)号：US11915136B1

公开(公告)日：2024-02-27

申请号：US17952852

申请日：2022-09-26

Applicant: Rambus Inc.

Inventor： Steven C. Woo

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.

公开(公告)号：US20240062788A1

公开(公告)日：2024-02-22

申请号：US18373162

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C7/08 ,  G11C5/025 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US11907555B2

公开(公告)日：2024-02-20

申请号：US17989838

申请日：2022-11-18

Applicant: Rambus Inc.

Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0635 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F13/1678 ,  Y02D10/00

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

公开(公告)号：US11900981B2

公开(公告)日：2024-02-13

申请号：US18078934

申请日：2022-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/00 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/00

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US20240045813A1

公开(公告)日：2024-02-08

申请号：US18236272

申请日：2023-08-21

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

CPC classification number: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).