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    AUTOMATIC RECONFIGURATION OF DEPENDENCY GRAPH FOR COORDINATION OF DEVICE CONFIGURATION
    61.
    发明申请
    AUTOMATIC RECONFIGURATION OF DEPENDENCY GRAPH FOR COORDINATION OF DEVICE CONFIGURATION 审中-公开

    公开(公告)号：US20190007263A1

    公开(公告)日：2019-01-03

    申请号：US15639363

    申请日：2017-06-30

    Applicant: Microsoft Technology Licensing, LLC

    Inventor： Shayak LAHIRI ,  Sean Anderson BOWLES ,  Peter J. KAUFMAN

    IPC: H04L12/24

    CPC classification number: H04L41/0803 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/142 ,  G06F11/1433 ,  G06F11/2247 ,  G06F11/2257 ,  H04L67/34

    Abstract: Various technologies described herein pertain to controlling reconfiguration of a dependency graph for coordinating reconfiguration of a computing device. An operation can be performed at the computing device to detect whether an error exists in the dependency graph for a desired configuration state. The dependency graph for the desired configuration state specifies interdependencies between configurations of a set of features. An error can be detected to exist in the dependency graph when the desired configuration state differs from an actual configuration state of the computing device that results from use of the dependency graph to coordinate configuring the set of features. Feedback concerning success or failure of the dependency graph on the computing device can be sent from the computing device to a configuration source. The dependency graph can be modified (by the computing device and/or the configuration source) based on whether an error is detected in the dependency graph.

    Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems
    64.
    发明授权
    Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems 有权

    公开(公告)号：US09612929B1

    公开(公告)日：2017-04-04

    申请号：US14994453

    申请日：2016-01-13

    Applicant: International Business Machines Corporation

    Inventor： Manoj Dusanapudi ,  Shakti Kapoor

    IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22

    CPC classification number: G06F11/263 ,  G06F11/2242 ,  G06F11/2247

    Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.

    INTERFACE INSERTION ANOMALY DETECTION CIRCUIT AND METHOD
    66.
    发明申请
    INTERFACE INSERTION ANOMALY DETECTION CIRCUIT AND METHOD 审中-公开
    接口插入异常检测电路和方法

    公开(公告)号：US20160349308A1

    公开(公告)日：2016-12-01

    申请号：US15114966

    申请日：2014-05-08

    Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

    Inventor： Jialiang Zhang ,  Kewei Wu ,  Jie Wu ,  Xingwei Yuan ,  Feiwu Shuai

    IPC: G01R31/04 ,  H04M1/24

    CPC classification number: G01R31/043 ,  G01R31/04 ,  G06F11/221 ,  G06F11/2247 ,  H02J2007/0062 ,  H04M1/24 ,  H04M1/72527

    Abstract: Provided are an interface insertion anomaly detection circuit and method applicable to the field of mobile terminals. The interface insertion anomaly detection circuit comprises a power circuit (4), and further comprises: a first USB interface (1), comprising a first power line and a first signal line, a power end of the first power line being connected to the power circuit (4); a second USB interface (2), comprising a second power line and a second signal line, the second power line and the second signal line being short-circuit connected, wherein the second USB interface (2) connects the second signal and the first signal line through insertion to the first USB interface (1); and a controller (3), a first voltage collection end and a second voltage collection end thereof being respectively connected to the power end of the first power line and a signal end of the first signal line. The controller (3) can determine, according to a calculated voltage difference, whether the first power line and the second power line are well connected by insertion, and then determine whether to start or resume charging a cell of a mobile terminal through the first USB interface (1) and the second USB interface (2).

    Abstract translation: 提供了适用于移动终端领域的接口插入异常检测电路和方法。 所述接口插入异常检测电路包括电源电路（4），还包括：第一USB接口（1），包括第一电力线和第一信号线，所述第一电力线的电源端连接到所述电源 电路（4）; 第二USB接口（2），包括第二电力线和第二信号线，所述第二电力线和所述第二信号线被短路连接，其中所述第二USB接口（2）将所述第二信号和所述第一信号 通过插入到第一个USB接口（1）; 和控制器（3），其第一电压采集端和第二电压采集端分别连接到第一电力线的电源端和第一信号线的信号端。 控制器（3）可以根据计算的电压差确定第一电力线和第二电力线是否通过插入良好连接，然后确定是否通过第一USB来启动或恢复对移动终端的小区充电 接口（1）和第二USB接口（2）。

    SYSTEMS AND METHODS FOR SELECTIVELY ENABLING AND DISABLING HARDWARE FEATURES
    67.
    发明申请
    SYSTEMS AND METHODS FOR SELECTIVELY ENABLING AND DISABLING HARDWARE FEATURES 审中-公开
    用于选择启用和禁用硬件特性的系统和方法

    公开(公告)号：US20160246596A1

    公开(公告)日：2016-08-25

    申请号：US15146781

    申请日：2016-05-04

    Applicant: International Business Machines Corporation

    Inventor： Susan K. Candelaria ,  John R. Paveza

    IPC: G06F9/22 ,  G06F9/445 ,  H04L29/06

    CPC classification number: G06F9/226 ,  G06F8/61 ,  G06F9/4411 ,  G06F9/468 ,  G06F11/2247 ,  G06F11/3051 ,  G06F11/327 ,  G06F13/22 ,  G06F13/426 ,  H04L41/02 ,  H04L65/102

    Abstract: In one embodiment, a computer program product includes a computer readable storage medium having stored/encoded thereon: first program instructions executable by a device to cause the device to define a hardware feature policy for one or more hardware components of a system; and second program instructions executable by the device to cause the device to enable and/or disabling one or more hardware features of one or more of the hardware components based on the hardware feature policy, where the hardware feature policy comprises instructions to enable and/or disable access to the one or more hardware features based on one or more criteria.

    Abstract translation: 在一个实施例中，计算机程序产品包括其上已经存储/编码的计算机可读存储介质：可由设备执行以使设备为系统的一个或多个硬件组件定义硬件特征策略的第一程序指令; 以及由所述设备执行以使得所述设备能够基于所述硬件特征策略来启用和/或禁用所述硬件组件中的一个或多个硬件组件的一个或多个硬件特征的第二程序指令，其中所述硬件特征策略包括使能和/或 基于一个或多个标准禁用对一个或多个硬件特征的访问。

    Systems for selectively enabling and disabling hardware features
    68.
    发明授权
    Systems for selectively enabling and disabling hardware features 有权
    选择启用和禁用硬件功能的系统

    公开(公告)号：US09400678B2

    公开(公告)日：2016-07-26

    申请号：US13797809

    申请日：2013-03-12

    Applicant: International Business Machines Corporation

    Inventor： Susan K. Candelaria ,  John R. Paveza

    IPC: G06F15/173 ,  G06F9/46 ,  H04L12/24

    CPC classification number: G06F9/226 ,  G06F8/61 ,  G06F9/4411 ,  G06F9/468 ,  G06F11/2247 ,  G06F11/3051 ,  G06F11/327 ,  G06F13/22 ,  G06F13/426 ,  H04L41/02 ,  H04L65/102

    Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor. The logic is adapted to: define a hardware feature policy for one or more hardware components of a system; and enable and/or disable one or more hardware features of one or more of the hardware components based on the hardware feature policy, wherein the hardware feature policy comprises instructions to enable and/or disable access to the one or most hardware features based on one or more criteria selected from a group consisting of: a feature access schedule; a volume feature access group; a job feature access group; and an user feature access group.

    Abstract translation: 在一个实施例中，系统包括与处理器集成和/或可执行的处理器和逻辑。 该逻辑适于：为系统的一个或多个硬件组件定义硬件特征策略; 以及基于所述硬件特征策略来启用和/或禁用所述硬件组件中的一个或多个的一个或多个硬件特征，其中所述硬件特征策略包括基于一个或多个硬件特征来启用和/或禁止访问所述一个或多个硬件特征的指令 或选自以下的组的更多标准：特征访问时间表; 卷功能访问组; 工作功能访问组; 和用户功能访问组。

    DETECTING DEVICE FOR DETECTING USB 2.0 SPECIFICATION AND ELECTRONIC APPARATUS WITH DETECTING DEVICE
    69.
    发明申请
    DETECTING DEVICE FOR DETECTING USB 2.0 SPECIFICATION AND ELECTRONIC APPARATUS WITH DETECTING DEVICE 审中-公开
    用于检测USB 2.0规格和检测设备的电子设备的检测装置

    公开(公告)号：US20160147625A1

    公开(公告)日：2016-05-26

    申请号：US14575828

    申请日：2014-12-18

    Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. ,  HON HAI PRECISION INDUSTRY CO., LTD.

    Inventor： JIE MIN ,  CHUN-SHENG CHEN

    IPC: G06F11/22 ,  G06F11/30 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F11/2247 ,  G06F11/3051 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A detecting device for detecting USB specification includes a USB interface circuit, a USB 2.0 detecting circuit, and a prompting circuit. The USB interface circuit includes a USB 2.0 pin for receiving data under USB 2.0 specification, and a USB 3.0 pin coupled to a south bridge chip for receiving data under USB 3.0 specification. The USB 2.0 detecting circuit is coupled to the USB 2.0 pin. The USB 2.0 detecting circuit can send a control signal to the prompting circuit upon detecting a data exchange requirement from the USB 2.0 pin. The prompting circuit can prompt upon receiving the control signal.

    Abstract translation: 用于检测USB规范的检测装置包括USB接口电路，USB 2.0检测电路和提示电路。 USB接口电路包括USB 2.0引脚，用于在USB 2.0规范下接收数据，以及一个USB 3.0引脚，连接到南桥芯片，用于接收USB 3.0规范下的数据。 USB 2.0检测电路耦合到USB 2.0引脚。 当USB 2.0引脚检测到数据交换要求时，USB 2.0检测电路可以向提示电路发送控制信号。 提示电路可以在接收到控制信号时提示。

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