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    Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated Circuit
    61.
    发明公开
    Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated Circuit 审中-公开

    公开(公告)号：US20240143885A1

    公开(公告)日：2024-05-02

    申请号：US17973078

    申请日：2022-10-25

    申请人： Google LLC

    发明人： Myung-Chul Kim ,  Roger David Carpenter ,  Debjit Sinha ,  Paul Kingsley Rodman ,  Xuyang Jin ,  Young-Joon Lee

    IPC分类号： G06F30/392 ,  G06F30/398

    CPC分类号： G06F30/392 ,  G06F30/398

    摘要： Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB), a block in the group is selected as a base block. The physical position of the base block is encoded in a reduced graph, and the physical positions of the remaining blocks are encoded as a linear transformation of the physical position of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be fed into a device configured to perform a circuit component placement process, to identify the placement of circuit components for blocks in the chip in accordance with one or more objectives.

    System and method for providing enhanced net pruning
    63.
    发明授权
    System and method for providing enhanced net pruning 有权

    公开(公告)号：US11972191B2

    公开(公告)日：2024-04-30

    申请号：US17334495

    申请日：2021-05-28

    申请人： Synopsys, Inc.

    发明人： Louis Schaffer ,  Timmy Lin ,  Soo Han Choi

    IPC分类号： G06F30/398 ,  G06F30/392

    CPC分类号： G06F30/398 ,  G06F30/392

    摘要： A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the marker layer is determined to exist. The marker layer, which is not stored in the connect database, designates a connection between at least a pair of nets in the circuit design.

    Timing error detection and correction circuit
    64.
    发明授权
    Timing error detection and correction circuit 有权

    公开(公告)号：US11971740B2

    公开(公告)日：2024-04-30

    申请号：US17335178

    申请日：2021-06-01

    申请人： NXP B.V.

    发明人： Roel Lieve P Uytterhoeven ,  Wim Dehaene

    IPC分类号： G06F1/08 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  H03K3/00 ,  H03K3/037 ,  H03K19/20 ,  G06F117/04 ,  H03K19/21

    CPC分类号： G06F1/08 ,  G06F30/392 ,  G06F30/394 ,  H03K3/037 ,  G06F2117/04 ,  H03K19/20 ,  H03K19/21

    摘要： An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.

    METHOD FOR RULE-BASED RETARGETING OF TARGET PATTERN
    67.
    发明公开
    METHOD FOR RULE-BASED RETARGETING OF TARGET PATTERN 审中-公开

    公开(公告)号：US20240126183A1

    公开(公告)日：2024-04-18

    申请号：US17769107

    申请日：2020-09-24

    申请人： ASML NETHERLANDS B.V.

    发明人： Ayman HAMOUDA

    IPC分类号： G03F7/00 ,  G06F30/392

    CPC分类号： G03F7/706839 ,  G03F7/70441 ,  G03F7/70625 ,  G06F30/392

    摘要： A method for generating a retargeted pattern for a target pattern to be printed on a substrate. The method includes obtaining (i) the target pattern comprising at least one feature, the at least one feature having geometry including a first dimension and a second dimension, and (ii) a plurality of biasing rules defined as a function of the first dimension, the second dimension, and a property associated with features of the target pattern within a measurement region; determining values of the property at a plurality of locations on the at least one feature of the target pattern, each location surrounded by the measurement region; selecting, from the plurality of biasing rules based on the values of the property, a sub-set of biases; and generating the retargeted pattern by applying the selected sub-set of biases to the at least one feature of the target pattern.

    METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND SYSTEM FOR DESIGNING INTEGRATED CIRCUIT
    69.
    发明公开
    METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND SYSTEM FOR DESIGNING INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240119213A1

    公开(公告)日：2024-04-11

    申请号：US18545268

    申请日：2023-12-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jian-Sing LI ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Ting-Wei CHIANG

    IPC分类号： G06F30/394 ,  G06F30/392

    CPC分类号： G06F30/394 ,  G06F30/392

    摘要： A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.