公开(公告)号：US09030257B2

公开(公告)日：2015-05-12

申请号：US13688671

申请日：2012-11-29

申请人： Sumitomo Electric Industries, Ltd.

发明人： Naoki Itabashi ,  Yoshiyuki Sugimoto ,  Makoto Ito ,  Keiji Tanaka

IPC分类号： H03F3/45 ,  H04B10/60

CPC分类号： H04B10/60 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2203/45166

摘要： A differential circuit with a function to compensate unevenness observed in the differential gain thereof is disclosed. The differential circuit provides a low-pass filter in one of the paired transistors not receiving the input signal in addition to another low-pass filter that provides an average of output signals as a reference level of the differential circuit. The cut-off frequency of the filter is preferably set to be equal to the transition frequency at which the self-heating effect explicitly influences the trans-conductance of the transistor.

摘要翻译： 公开了一种补偿其差分增益中观察到的不均匀性的差分电路。 除了提供输出信号的平均值作为差分电路的参考电平的另一个低通滤波器之外，差分电路在一个未被接收输入信号的成对晶体管之一中提供低通滤波器。 滤波器的截止频率优选设定为等于自发热效应显着地影响晶体管的跨导的转变频率。

公开(公告)号：US08717105B2

公开(公告)日：2014-05-06

申请号：US13379126

申请日：2010-06-10

申请人： Haruhiro Funakoshi ,  Shinya Ito

发明人： Haruhiro Funakoshi ,  Shinya Ito

IPC分类号： H03F3/08

CPC分类号： H03F3/082 ,  G01J1/46 ,  H03F1/02 ,  H03F3/087 ,  H03F3/3022 ,  H03F3/45192 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/264 ,  H03F2200/411 ,  H03F2203/45166 ,  H03F2203/45174 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45536

摘要： A photodetecting device 1 includes a photodiode PD and an integrating circuit 11. The integrating circuit 11 includes an amplifier circuit 20, a capacitive element C2, and a second switch SW2. The amplifier circuit 20 has a driving section including a PMOS transistor T1 and an NMOS transistor T2, the respective drain terminals thereof being connected to each other. A first switch SW1 comprising a PMOS transistor T10 is opened or closed according to the level of a first reset signal Reset1 input to the gate terminal. When the first reset signal Reset1 is at a low level, the first switch SW1 is closed to apply a power supply potential VDD to the gate terminal of the PMOS transistor T1, thereby turning off the PMOS transistor T1. Thus, an amplifier circuit, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

摘要翻译： 光检测器件1包括光电二极管PD和积分电路11.积分电路11包括放大器电路20，电容元件C2和第二开关SW2。 放大器电路20具有包括PMOS晶体管T1和NMOS晶体管T2的驱动部分，其各个漏极端子彼此连接。 包括PMOS晶体管T10的第一开关SW1根据输入到栅极端子的第一复位信号Reset1的电平而断开或闭合。 当第一复位信号Reset1处于低电平时，第一开关SW1闭合，以向PMOS晶体管T1的栅极端施加电源电位VDD，从而关断PMOS晶体管T1。 因此，可以实现能够实现低功耗和高速度的放大器电路，积分电路和光电检测装置。

公开(公告)号：US08421541B2

公开(公告)日：2013-04-16

申请号：US12606003

申请日：2009-10-26

申请人： Susanta Sengupta ,  Kenneth C. Barnett

发明人： Susanta Sengupta ,  Kenneth C. Barnett

IPC分类号： H03F3/04

CPC分类号： H03F1/3211 ,  H03F1/3223 ,  H03F3/45188 ,  H03F2203/45024 ,  H03F2203/45166 ,  H03F2203/45318 ,  H03F2203/45366

摘要： Techniques for designing a highly differential single-ended-to-differential converter for use in, e.g., communications receivers. In an exemplary embodiment, an auxiliary current path including cascomp transistors is coupled to a main current path including input transistors and cascode transistors. The transistors are biased such that inter-modulation products generated by the auxiliary current path cancel out inter-modulation products generated by the main current path. In another exemplary embodiment, current source transistors for the main current path are adaptively biased depending on the level of the input signal received. In an exemplary embodiment, the techniques may be applied to designing a converter for interfacing a single-ended low-noise amplifier (LNA) output voltage with a differential mixer input in a communications receiver.

摘要翻译： 用于设计用于例如通信接收机的高差分单端到差分转换器的技术。 在示例性实施例中，包括cascomp晶体管的辅助电流路径耦合到包括输入晶体管和共源共栅晶体管的主电流路径。 晶体管被偏置，使得由辅助电流路径产生的互调产物抵消由主电流路径产生的互调产物。 在另一个示例性实施例中，用于主电流路径的电流源晶体管根据所接收的输入信号的电平自适应地偏置。 在示例性实施例中，这些技术可以应用于设计用于将单端低噪声放大器（LNA）输出电压与通信接收机中的差分混合器输入接口的转换器。

公开(公告)号：US20110241777A1

公开(公告)日：2011-10-06

申请号：US13077099

申请日：2011-03-31

申请人： Makoto Ito ,  Sosaku Sawada

发明人： Makoto Ito ,  Sosaku Sawada

IPC分类号： H03F3/45 ,  H03F1/22

CPC分类号： H03F3/45089 ,  H03F2203/45166 ,  H03F2203/45702

摘要： A differential amplifier showing a suppressed output offset is disclosed. The differential amplifier includes a pair of differential transistors, a pair of cascode transistors, and a reference generator. One of differential transistors receives an AC signal, while, the other of differential transistors receives an average voltage of the AC signal. The reference generator receives the average voltage of the AC signal and outputs a bias commonly provided to the cascode transistor. The bias is raised by a substantially constant level from the average voltage, which compensates the output offset of the differential amplifier.

摘要翻译： 公开了一种显示抑制输出偏移的差分放大器。 差分放大器包括一对差分晶体管，一对共源共栅晶体管和参考发生器。 差分晶体管中的一个接收AC信号，而另一个差分晶体管接收AC信号的平均电压。 参考发生器接收AC信号的平均电压，并输出通常提供给共源共栅晶体管的偏置。 偏置电压从平均电压提高到基本恒定的水平，这补偿了差分放大器的输出偏移。

公开(公告)号：US07777663B2

公开(公告)日：2010-08-17

申请号：US12261704

申请日：2008-10-30

申请人： Taiji Akizuki ,  Tomoaki Maeda ,  Hisashi Adachi

发明人： Taiji Akizuki ,  Tomoaki Maeda ,  Hisashi Adachi

IPC分类号： H03M1/12

CPC分类号： H03F3/45475 ,  H03F3/45183 ,  H03F3/45946 ,  H03F2200/411 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03F2203/45421 ,  H03F2203/45424 ,  H03F2203/45512 ,  H03F2203/45551 ,  H03F2203/45634 ,  H03M1/1245

摘要： The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).

摘要翻译： 本发明旨在在离散时间放大器电路和AD转换器中实现简化的电路配置和低电流消耗，以改善从瞬态响应状态到放大器电路的稳定状态的收敛，并且由于 输出共模电压的变化。 离散时间放大器电路和AD转换器配备有开关电容共模反馈（CMFB）电路，其能够在电路以双倍采样的情况下在每个采样定时检测和反馈输出共模电压 时间（每½周期）。

公开(公告)号：US20100066436A1

公开(公告)日：2010-03-18

申请号：US12212486

申请日：2008-09-17

申请人： Chun C. Lee

发明人： Chun C. Lee

IPC分类号： H03K3/01

CPC分类号： H03F3/45183 ,  H03F1/0261 ,  H03F3/005 ,  H03F2203/45166 ,  H03F2203/45244 ,  H03F2203/45321 ,  H03F2203/45461 ,  H03F2203/45466 ,  H03F2203/45471 ,  H03F2203/45512 ,  H03F2203/45551 ,  H03F2203/45561 ,  H03F2203/45616 ,  H03F2203/45674

摘要： Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.

摘要翻译： 本公开的示例性实施例包括自适应地产生开关电容器电路的偏置电流。 示例性装置包括以采样率操作的第一相位信号和第二相位信号。 第一相位信号的断言时间和第二相位信号的断言时间被隔开预定义的非重叠时间。 该装置还包括具有可操作地耦合到第一相位信号和第二相位信号的多个开关电容器的开关电容器电路。 放大器可操作地耦合到开关电容器电路并具有与自适应偏置电流成反比的响应时间。 偏置发生器耦合到放大器并且操作以响应于第一相位信号的断言时间来修改自适应偏置电流。

公开(公告)号：US07619478B2

公开(公告)日：2009-11-17

申请号：US12042567

申请日：2008-03-05

申请人： Koji Yamazaki ,  Takeki Ebina

发明人： Koji Yamazaki ,  Takeki Ebina

IPC分类号： H03F1/14

CPC分类号： H03K5/2481 ,  H03F1/086 ,  H03F3/45183 ,  H03F3/4521 ,  H03F3/45475 ,  H03F2203/45166 ,  H03F2203/45248 ,  H03F2203/45514 ,  H03K5/249

摘要： An operational amplifier includes a differential amplifier connected between an input and an output port of the operational amplifier, a phase compensator capacitance connected between the differential amplifier and the output port, a switching transistor for controlling the connection between the phase compensator capacitance and the differential amplifier, a detection transistor responsive to a potential difference between the input and output ports to be rendered conductive, and a control transistor responsive to the detection transistor for controlling the switching transistor. The operational amplifier has its slew rate improved without detracting from stability against oscillation and continuity of the output waveform.

摘要翻译： 运算放大器包括连接在运算放大器的输入和输出端口之间的差分放大器，连接在差分放大器和输出端口之间的相位补偿器电容器，用于控制相位补偿器电容和差分放大器之间的连接的开关晶体管 响应于要导通的输入和输出端口之间的电位差的检测晶体管，以及响应于用于控制开关晶体管的检测晶体管的控制晶体管。 运算放大器的转换速率得到改善，而不会降低稳定性，避免振荡和输出波形的连续性。

公开(公告)号：US07613943B2

公开(公告)日：2009-11-03

申请号：US11931772

申请日：2007-10-31

申请人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kolkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

发明人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kolkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

IPC分类号： H03K19/173 ,  G06F1/30

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

公开(公告)号：US20090267694A1

公开(公告)日：2009-10-29

申请号：US12108034

申请日：2008-04-23

申请人： MIchael Wendell VICE

发明人： MIchael Wendell VICE

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45342 ,  H03F2203/45604 ,  H03F2203/45702

摘要： An apparatus includes an input-bias node and an internal load. The input-bias node is configured to simultaneously receive an input signal and a bias signal through an input-bias port. The internal load is connected between the input-bias node and multiple output ports, at least one of the output ports outputting an output signal based on the input signal received at the input-bias node.

摘要翻译： 一种装置包括输入偏置节点和内部负载。 输入偏置节点被配置为通过输入偏置端口同时接收输入信号和偏置信号。 内部负载连接在输入偏置节点和多个输出端口之间，至少一个输出端口基于在输入偏置节点处接收的输入信号输出输出信号。

公开(公告)号：US07560952B2

公开(公告)日：2009-07-14

申请号：US12028615

申请日：2008-02-08

申请人： Limin Zhu ,  Theodore Speers ,  Gregory Bakker

发明人： Limin Zhu ,  Theodore Speers ,  Gregory Bakker

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a state machine controls the saving of states of various volatile memories and registers to the non-volatile memory and also controls the initialization of the volatile registers and memories using the saved state data.

摘要翻译： 集成电路装置具有省电特征，并且包括可编程逻辑块，I / O焊盘，专用寄存器，至少一个易失性存储器块，非易失性存储器块，用于检测至少一个 条件，诸如状态机的控制电路控制各种易失性存储器和寄存器的状态的保存到非易失性存储器，并且还使用保存的状态数据来控制易失性寄存器和存储器的初始化。